The S3ADSD1M16BT180 is a compact and low power Continuous-Time Sigma-Delta ADC with an input Signal Bandwidth of 500kHz.
This IP includes a first-order Anti-Aliasing filtering function. Noise Shaping is implemented with a 3rd Order Modulator.
Working at 128MHz clock frequency, this ADC features an outstanding performance that includes 84.0dB SNDR, -90dB THD and 13.7-bit ENOB.
Excluding the Digital Decimation filter, the supply current is only 1.4mA and occupies only 0.4mm2 area.
The S3ADSD1M16BT180 does not require any special analog process options.
- TSMC 180nm Process
- No Analog Options
- 1.8V Supply
- Continuous-Time Sigma-Delta ADC
- Built-In 1st Order Anti-Aliasing Filter
- 500kHz Input Signal Bandwidth
- 128MHz Output Bitstream
- 128MHz Input Clock Frequency
- Input Signal Range: 2.0Vppdiff
- Outstanding Performance:
- -90.0dB THD
- 84.0dB SNDR
- 13.7-bit ENOB
- Low Power Dissipation:
- 1.4mA Total Supply Current
- Compact Die Area: 0.4mm2
- (Decimation Filter not included)
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
- Industrial IoT
- Motion and Environmental Sensing
- Motor Control
- Home Automation
- Consumer Electronics
Block Diagram of the 500kHz Bandwidth CTSD ADC IP Core