56Gbps Long Reach SerDes IP for TSMC 7nm

The Cadence® 56Gbps Long Reach Quad-Lane SerDes IP for TSMC 7nm operates at a full-rate of 56Gbps using PAM-4 modulation, as well as 28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links.

The multi-rate PHY IP supports primary Ethernet data rates within +/- 200ppm. An integrated microcontroller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address).

There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings. The Channel Estimator hardware allows the accurate measurement of the channel response to assess package, connector, and trace characteristics

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