Time Sensitive Networking (TSN) refers to a suite of IEEE standards defining highly deterministic and redundant networking operation for control and other latency sensitive traffic in Ethernet networks. TSN defines traffic streams that can be scheduled through time-aware shapers to meet stringent performance guarantees such as bounded latency, latency variation, and minimal loss of packets. The VSC9956-01 TSN switch core IP supports either cut-through or store-and-forward switching of scheduled traffic, which can be protected with intelligent guard banding. To provide a high level of reliability, the IP core is designed to avoid hash table conflicts for this traffic.
The scheduled traffic and redundancy capabilities of this switch IP provide more deterministic per-hop latency, higher probability of initial packet delivery, and seamless clock synchronization across redundant paths in a network. The IP core supports both IEEE 802.1AS and IEEE 802.1ASbt to provide precise time synchronization of the network nodes to a reference time by synchronizing distributed local clocks with a reference. IEEE 802.1ASbt support includes one-step time stamping and pre-selected failover grand master clock support.
In addition, the IP core supports a set of earlier specifications known as Audio Video Bridging (AVB) standards, which collectively provide low-latency, time synchronized services for audio/video streaming applications. The AVB specifications include Stream Reservation Protocol (SRP) [IEEE 802.1Qat], Timing and Synchronization for Time Sensitive Applications [IEEE 802.1AS], and Forwarding and Queuing Enhancements for Time-Sensitive Streams [IEEE 802.1Qav] for streaming traffic class applications, such as automotive camera and infotainment applications. The Stream Reservation (SR) class observation interval of this IP core has the flexibility to be programmed to support greater than Class B intervals to support various application requirements.
The VSC9956-01 switch IP core supports VLAN classification and translation with pattern matching against Layer 2 through Layer 4 information including MAC addresses, VLAN tag headers, EtherType, DSCP, IP addresses, and TCP/UDP ports and ranges. VLAN translation can be processed on ingress and/or egress.
The switch core supports wire-speed, hardware-based learning, and CPU-based software learning that is configurable per port. Secure CPU-based learning is an available option.
A comprehensive application programming interface (API) is also available for the VSC9956-01 switch IP core.
- Time Sensitive Networking (TSN)
- Audio Video Bridging (AVB)
- Advanced TCAM-based Quality of Service (QoS) and security
- Configurable watermarks per CoS, per port
- VLAN translation
- Priority-based flow control (IEEE 802.1Qbb)
- Energy Efficient Ethernet (IEEE 802.3az)
- IP deliverables for ASSP/ASIC