The S3ADS750M8BT65LPB is a compact and ultra low power 8-bit High-Speed SAR ADC IP with a sampling rate up to 750MS/s.
This 8-bit ADC features an outstanding dynamic performance that includes -48.0dB THD, 47.2dB SNR and 7.0-bit ENOB (noise integrated up-to Nyquist).
The static performance includes <±1.0LSB INL and <±0.8LSB DNL (No Missing-Codes).
- TSMC 65nm LP Process
- No Analog Options
- 1.2V Single Supply
- 8-bit High-Speed SAR ADC
- Sampling Rate up to Fs=750MS/s
- Input Clock up to Fclk=1.125GHz (Fclk = 1.5 x Fs)
- Power Scales with Sampling Rate
- Fully Differential Input Signal
- Input Signal Range: 1.2Vppdiff
- Outstanding Static Performance:
- DNL < ± 0.8 LSB (no Missing-Codes)
- INL < ± 1.0 LSB
- Outstanding Dynamic Performance:
- 47.2dB SNR
- -48.0dB THD
- 43.8dB SNDR
- 7.0-bit ENOB
- [Noise integrated up-to Nyquist]
- Low Power Dissipation: 15mW
- Compact Die Area: 0.2mm2
- Considering a 750MS/s sampling rate, this ADC power dissipation is only 15mW. This power reduces linearly with the clock frequency scaling.
- The S3ADS750M8BT65LPB Die Area is only 0.2mm2 and it does not require any special analog process options.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog)
- Integration Support
- Wireless Communications
- Wireline Communications
- Servo Channels for Tape Drive Products
- Read Channels for Serial-Link Systems
Block Diagram of the 8-bit 750MS/s SAR ADC IP Core