8-bit SAR ADC_SMIC_65_LL
Features
- 1. Time interleaved architecture for excellent dual channel matching performance.
- 2.Programmable maximum differential input from 0.5Vdpp to 1.0Vdpp.
Benefits
- 1. Internal reference
- 2. Compact Die Area
Deliverables
- 1.Datasheet
- 2.Flat Netlist (cdl)
- 3.Layout View (gds2)
- 4.Abstract View (lef)
- 5.Timing View (lib)
- 6.Behavioral Model (Verilog)
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