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9 track standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF Sesame 9T a unique architecture based on 9-track cells, optimized for High Density and Low Dynamic Power allowing users to create faster SoC than with 7-track libraries.
Features
- Compromise for density and speed9-Track high cells
- Only Metal 1 used for cell design
- Compatible with 1P3M SoC implementationwith island construction kit
View 9 track standard cell library at TSMC 55 nm full description to...
- see the entire 9 track standard cell library at TSMC 55 nm datasheet
- get in contact with 9 track standard cell library at TSMC 55 nm Supplier
Standard cell IP
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 7 track Ultra High Density standard cell library at TSMC 28 nm
- 7 track Ultra High Density standard cell library at TSMC 28 nm HPC+