English
Browse >>
X
Browse by category
-
Analog & Mixed Signal (5594)
-
Memory Controller & PHY (755)
-
Graphic & Peripheral (468)
-
Interface Controller & PHY (2275)
-
Processor Solutions (723)
-
Memory & Logic Library (5565)
-
Security (447)
-
Multimedia (612)
-
Wireline Communication (886)
-
Wireless Communication (413)
-
Automotive (46)
-
Platform Level IP (84)
- Network-on-Chip (NoC) (21)
-
Other (904)
Browse by Provider
Browse by Foundry
New Silicon IP
-
Multichannel module supporting ARINC429 Receiver/Transmitter
- Multichannel module supporting ARINC429 Receiver/Transmitter.
- Configurable module supporting any number of receivers and transmitters
-
PHY IP for PCIe 6.0 in TSMC N5
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
- Supports PCIe Lane Margining at Receiver
-
Generic Waveform Generator
- Scalable approach
- Huge set of supported protocols
- Variable set of driver ans stimuli units possible
-
IP cores for Edge AI in XR devices
- Ultra-fast Response Time
- Zero-latency Switching
- Low Power
-
Charge Pump with ULP Ludicrous Mode on GF 22FDSOI
- Fast response Charge Pump
- Output current up to 100mA
- Ludicrous Low Power Mode
-
Ultra-Low Phase Noise Digital LC PLL
- Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
-
AV1/HEVC/AVC Dual-core Video IP
- High-quality encoding
- Bandwidth efficiency
- Low delay encoding
-
Automotive-Grade MIPI DSI-2 Controller IP
- Complete single-vendor solution for mobile and mobile-influenced applications
- Proven MIPI CSI-2, DSI and I3C controllers
- Silicon-proven D-PHY and M-PHY
-
Open RAN Platform for Base Station and Radio
- Fully configurable comprehensive IP platform for 5G NR and multi-mode RAT addressing both Basestation and Radio Open RAN use cases
-
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
- Compression ratio: 2-4x across diverse data sets
- Compression throughput: 8GB/s
- Decompression throughput: 10.5GB/s
-
Universal IoT Security Platform
- Easy for the end-user
- Private key lifecycle
- Versatile integration
-
Synopsys USB3.2 PHY IP on Samsung 4LPE
- Supports 20Gbps, 10Gbps, and 5Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
Top Silicon IP
-
1
UCIe Controller
- Low Latency controller for UCIe-based die-to-die connectivity
- Includes Die-to-Die Adapter layer and Protocol layer
-
2
32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets
- 32-bit RISC-V ISA
- ASIL B and ASIL D area optimised product variants
- Functional Safety Package and Independent Assessment
-
3
PCIe 5.0 PHY
- Advanced, built-in diagnostics including on-chip digital RX eye scope
- Internal/external loopback
- 8b/10b and 128b/130b encoding and decoding
-
4
UCIe PHY IP for TSMC N5
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
-
5
RISC-V 64-bit Standard CPU
- Efficient Out of Order Superscalar w/ hardware-multithreading
- High Performance Vector Processing Unit (Optional)
-
6
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
- Compression ratio: 2-4x across diverse data sets
- Compression throughput: 8GB/s
- Decompression throughput: 10.5GB/s
-
10
12-bit SAR ADC TSMC
-
11
Bi-Directional LVDS with LVCMOS
-
12
Ultra-Low Phase Noise Digital LC PLL
- Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
¹ Top Silicon IP Over the Last Two Weeks (Last update: Oct. 2)
IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Silicon IP catalog (8,000 products from more than 400 companies)