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Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC X-FAB

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New Silicon IP

• Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (up to 3.63V input supply)

  • Low leakage current for best consumption in sleep mode
  • High PSRR to supply analog loads
  • Support input supply voltage up to 3.63V
  
   
  
  

• 64-bit CPU with RISC-V Vector Extension

  • AndeStarâ„¢ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
  • RISC-V vector extension
  
   
  
  

• XBC OTP NVM IP for TSMC 16FFC, 1.8V

  • Retention exceeding 10 years
  • Standard CMOS process
  • Highly secure
  
   
  
  

• MIPI D-PHY CSI-2 TX for TSMC 22ULL

  • Supports MIPI Alliance Specification for D-PHY Version 2.5
  • Consists of 1 Clock lane and 1 Data lane
  
   
  
  

• MIPI D-PHY Rx ONLY v1.1 @1.5ghz Ultra Low Power & Low Area for IoT & Wearables

  • Compliant with MIPI D-PHY Specification v2.5 with backwards compatibility for D-PHY v2.1, v1.2, and v1.1
  
   
  
  

• Low Drop Out Capless 5mA Voltage Regulator

  • 40nm TSMC Low Power Process, 6 Metals Used (No Analog Options) with Deep-Nwell
  • 2.4V – 3.6V Input Voltage
  • 1.1V 2.5% Output Voltage
  
   
  
  

• High Performance, Low Latency PCIe Gen5 PHY

  • 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
  • Tight skew control of less than 1UI between lanes of the PMA
  
   
  
  

• 40Gbps MP SerDes PHY (PCIe Gen1-5) 7nm

  • 1 - 40 Gbps continuous operation
  • World’s best power, area and latency in segment
  • Channel loss support up to 25dB
  
   
  
  

• Ultra Low Phase Noise Driver

  • Revolutionary Ultra Low Phase Noise operation
  • Ultra Low Power Operation
  • RF front end sensitivity enhancement
  
   
  
  

• Inline Decrypter IP Core

  • XIP (eXecution In Place) of encrypted code directly from Flash. (Optional xSPI controller)
  • Decryption based on AES fully compliant with NIST FIPS 197
  • AMBA Master/Slave interfaces
  
   
  
  

• MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables

  • Compliant with MIPI D-PHY Specification v2.5 with backwards compatibility for D-PHY v2.1, v1.2, and v1.1
  
   
  
  

• HDMI 2.1 Transmitter (TX) PHY IP for GF 12LP

  • HDMI 2.1 TX IP solution includes PHYs, controllers, verification IP
  • Compliant with the HDMI 2.1, 2.0, 1.4 and HDCP 2.2, 1.4 specifications
  
   
  
  

Top Silicon IP

• 1

  Scalable Cache Coherency

  • Quasi-linear speedup with respect to the number of cores.
  • Area-efficient with a Coherency area impact <2% for 34 Mbyte caches for 96 cores
  
   
  
  
• 2

  Asynchronous Network on Chip IP

  • High performance interconnects, Ultra-low-latency and Deep pipelining
  
   
  
  
• 3

  64-Bit RISC-V High Performance Processor

  • RISC-V RV64 I/M/A/C/F/D/P ISA supported
  • ECLIC（Enhanced Core Level Interrupt Controller）
  • 6-Stage Pipeline
  
   
  
  

• 4

  PUFrt-based secure storage supports XIP

  • Integrated, secure embedded Flash solution built from adding an embedded Flash to PUFrt
  
   
  
  
• 5

  Bluetooth Controller

  • Integrates Bluetooth 5 Link Layer and/or IEEE 802.15.4 MAC
  • Shares resources (memory, combo fabric) for area optimization
  
   
  
  
• 6

  Complete Neural Processor for Edge AI

  • Designed for Low-Power Neural Network Processing
  • Flexible Training Methods
  • Scalable Neuron Fabric
  
   
  
  

• 7

  Fractional-N Frequency Synthesizer PLL (3nm - 180nm)

  • 1MHz up to 1.6GHz input frequency range
  • 1MHz up to 3.6GHz output frequency range
  • 24 bit fractional resolution
  
   
  
  
• 8

  PHY IP for PCIe Express 4.0 in TSMC N6

  • Compliant with PCIe® 4.0, 3.1, 2.1, 1.1, and PIPE specifications
  • x1, x2, x4, x8, x16 lane configurations with bifurcation
  
   
  
  
• 9

  RISC-V-based SoC template

  • Based on the picorv32 RISC-V CPU
  • (Re)programmable via UART
  
   
  
  

• 10

  Voltage Optimization Modules

  • Proven 28nm FDSOI implementation
  • Timing Fault Sensor
  • Timing Fault Ring
  
   
  
  
• 11

  Super Inductor IP

  • High Inductor Q (10 to 50)
  • High Inductor Bandwidth (2.5Ghz to 50Ghz)
  • Stackable Design
  
   
  
  
• 12

  14-Bit 12MHz Bandwidth Continuous Time Sigma Delta ADC on UMC 40nm

  • UMC 40nm LP Process
  • 1.1V Supply
  • Continuous-Time Sigma-Delta ADC
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: Jan. 24)

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