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CryoCMOS IP to Unlock Quantum Computing

• Specially Engineered CryoCMOS IP
• Characterised down to 4°K
• Minimal Power Dissipation

VESA DisplayPort 2.0 FEC TX

• VESA DisplayPort 2.0 compliant
• Reed-Solomon RS(198,194) FEC, 8-bit symbols
• Multiple symbols per clock

IEEE 1914.3 RoE Structure Agnostic Mapper/Demapper

• Complies with IEEE 1914.3 standard
• Supports multiple streams of CPRI and Ethernet
• Complies with CPRI 7.0 standard

LPDDR54 PHY on Samsung Foundry 14nm

• JESD209-5A(LPDDR5), JESD209-4C(LPDDR4), JESD209-4-1(LPDDR4X) compliant
• Operating speed up to 6400Mbps in LPDDR5, 4266Mbps in LPDDR4X
• Multiple DFICLK : CK :WCK ratios

HBM3 Controller

• JEDEC HBM 3.0 DRAM
• DFI 5.0 complaint interface to HBM3 PHY
• Multiport Arm® AMBA® interface (4 AXI AXIâ„¢) with managed QoS or single-port host interface, per pseudo-channel

PCIe Gen3 PHY

• Low Risk - Silicon proven with Si characterization data
• Excellent Interoperability
• Superior Noise Immunity

NIST-Certified Random Number Generator, software-only implementation using SRAM start-up values as source of randomness

• Uses standard SRAM start-up values as a true random source
• NIST CAVP certified for DRGB and AES
• Compliant with NIST SP 800-90

I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion

• Integrating this unique component will eliminate a discrete component in the bill of materials
• Support for both FPGA and ASIC with seamless transition

400G/800G Ethernet PCS IP

• Configurable, multi-rate solution supporting Ethernet data rates from 1G to 800G

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver

• One clock lane and four data lanes.
• Up to 2.5Gbps per lane.
• Support of all CSI2 primary and secondary data formats.

Analog-PLL For Frequency Multiplying

• Process: TSMC 28nm HPM/HPC
• Available metalization technologies: 4X2Y2R and 5X2Y2R

MIPI Soundwire PHY

• MIPI specification for SoundWire V1.2
• TSMC 12nm FFC

Image Signal Processor

• Gamma correction
• 3A(AWB/AE/AF)
• Black level compensation

Bunch of Wires [BoW] PHY

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI

• 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process

Graphics Processor Overlay IP Core

• Technology independent soft IP Core for FPGA, ASIC and SoC devices
• Supplied as human-readable VHDL (or Verilog) source code

400G/800G Ethernet MAC IP

• Configurable, multi-rate solution supporting Ethernet data rates from 1G to 800G

PHY IP for PCIe 6.0 in TSMC N5

• Supports the latest features of PCIe 6.0 specification
• Supports PAM-4 signaling and up to x16 lane configurations with bifurcation

TSMC CLN28HPC+ 28nm DDR 4/3 PHY - 3200Mbps

• Supports DDR4-3200, DDR3/L/U, LPDDR4/X and LPDDR3, simultaneously with one hard macro
• DFI 4.0 compliant

10-bit, 12-bit, 14-bit, Low Speed SAR ADC in TSMC (180nm, 90nm, 55nm, 40nm, 28nm, 16nm, 12nm)

Fractional-N Frequency Synthesizer PLL (3nm - 180nm)

• 1MHz up to 1.6GHz input frequency range
• 1MHz up to 3.6GHz output frequency range
• 24 bit fractional resolution

NVMe Host Controller

• NVMe host controller with AXI control and data path interfaces
• Supports vendor-specific PCIe hard IP
• Supports PCIe soft IP

VESA DisplayPort 2.0 FEC RX

• VESA DisplayPort 2.0 compliant
• Reed Solomon RS (198,194) FEC, 8-bit symbols
• Multiple symbols per clock

PHY IP for Bluetooth low energy, Thread, and Zigbee in TSMC (40nm, 55nm)