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Ultra low power AI inference accelerator

Integrated Secure Element (iSE)

• Secure boot
• Life cycle management
• Secure key storage

25Gbps Ethernet and CPRI-10 FEC Layer IP Core

• Proven IP reduces development time and risk
• Upgrade process as the standard evolves
• Supports both 25GBASE-KR and 25GBASE-CR PMD interfaces

12-bit 500MS/s Dual Channel IQ ADC

• Samsung 8nm LPP Process
• 0.75V and 1.8V Supplies
• 12-bit High-Speed SAR Dual-Channel ADC

MIPI C-PHY/D-PHY IP for TSMC 12FFC

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 4.5 Gb/s per lane
• Compliant with the MIPI C-PHY specification, v1.2

High performance FFT optimised for Radar

• 1 clock cycle per point, no gap required between packets
• Run-time selection of any power of 2 FFT points
• Run-time selection of froward or inverse transform

MIPI D-PHY Universal IP in Samsung 28FDSOI

• Supports MIPI® Specification for D-PHY Version 2.1.
• Consists of 1 Clock lane and up to 4 Data lanes.
• Supports both high speed and low-power modes.

Wideband LNA with a gain adjustment range from -22 to 20dB

• TSMC SiGe BiCMOS 180 nm
• Operating frequency range 500…1500 MHz
• Low noise figure (2 dB)

Camera SLVS-EC/MIPI D-PHY/CMOS1.8 combo Receiver 2.4G/2.5G/166MHz 8-Lane

• SLVS-EC ver.1.2 / MIPI D-PHY ver.1-2 compliant
• Supporting for four kind Differential Input Signals
• Xtal Input Clock Frequency Selectable

DDR5/4 PHY IP for TSMC 12FFC

• TSMC 12FFC
• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 4800 Mbps

Power On Reset Circuit with RC-Oscillator

• TSMC 40nm ULP
• Power-on Reset output
• Two power domains (3.3V, 1.1V) monitoring

All Digital Fractional-N PLL for Low-Jitter Clocking

• Frequencies up to 4GHz
• Low jitter (< 10ps RMS)
• Small size (< 0.01 sq mm)

MIMO Radar Co-processor Engine

• Low latency, low power and compact
• Gives ECU headroom for track-to-object recognition and make safety decisions

Linux capable 64-bit RISC-V processor core with 7-stage pipeline

• 64-bit RISC-V core
• Linux capable
• In-order 7-stage pipeline

High Performance PLL in TSMC 7nm

• Fully SCAN enabled
• Fully customizable to each application
• Wide operating voltages available for DVFS

LPDDR5/4/4X PHY IP

• TSMC 12FFC
• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps

DesignWare MIPI C-PHY/D-PHY IP for TSMC N7

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 4.5 Gb/s per lane
• Compliant with the MIPI C-PHY specification, v1.2

Free-running on-chip oscillator

• Glitch-free frequency programmability to calibrate out process variations Frequency accuracy as good as 1.5% over voltage, temperature, and process aging after initial calibration

10-bit SAR ADC TSMC

• Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
• Quick re-configuration to your specification
• Up to 10-bit resolution

12-bit 90MS/s ultra-efficient SAR ADC in UMC 28nm HPC+

• UMC 28nm HPC+
• Robust Performance
• Low Power
• Low Area

HBM3 Controller

• Supports HBM3 protocol standard draft JEDEC specification.
• Compliant with DFI version 4.0 and 5.0 Specification.
• Supports up to 16 AXI ports with data width upto 512 bits.

Power Management Unit (2.3 - 3.0V output voltage, load current 150mA)

• iHP SiGe BiCMOS 0.13 um
• Output voltage: 2.3 ... 3.0 V
• Overcurrent indication

All Digital Fractional-N PLL for Low-Jitter Clocking

• Frequencies up to 4GHz
• Low jitter (< 10ps RMS)
• Small size (< 0.01 sq mm)

Low Power PLL

• Lowest power in the industry
• Smallest area in the industry
• Customizable in weeks