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32-bit IP Listing

1273 IP Cores (441 - 480)

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PCIE 4.0 PHY SSMIC14SF+/smic12SFE

The Innosilicon PCIE4.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE4.0 Super-Speed standard from Intel. ...

441
STS48/STM16 Framing/TOH/POH/Concatenated Pointer Processing to STS48c level

The Xelic SONET/SDH Concatenated STS-48c/STM-16 Framer Core (XCS48C) aligns incoming SONET/SDH frames and provides transport overhead processing, path overhead processing and pointer processing ...

442
10Gbit/s OTN RS(255,239) Encoder

The Xelic OTN 10Gb/s FEC Encoder (XCO2FECE) core generates interleaved Reed Solomon (255,239) codes for Optical Transport Network applications. Interleaving is performed as outlined in specification ...

443
2.5Gbit/s OTN RS(255,239) Decoder

The Xelic OTN 2.5Gb/s FEC Decoder (XCO1FECD) core detects and corrects incoming errors using interleaved Reed Solomon (255,239) codes for Optical Transport Network applications. Interleaving ...

444
DDR3/DDR2 Memory Controller

The IPX-DDR2 core is a DDR2 memory controller for Xilinx devices running up to 266 MHz and with bus width of up to 64 bits. This intoPIX core reduces the number of logic resources and improves ...

445
I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AXI System Interconnect Fabric to an I2C Bus. ...

446
Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO

The Hs-Mode I2C Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode ...

447
Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO

The Hs-Mode I2C Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode ...

448
10-Gbps Ultra-Low Latency Ethernet MAC & PCS (10GBASE-R)

The Ultra-Low Latency Ethernet MAC and PCS is the ideal core for latency critical applications. These IP cores are designed to minimize congestion, to eliminate high fan-out nets, and to ...

449
40-Gbps Ultra-Low Latency Ethernet MAC & PCS (40GBASE-R4)

The Ultra-Low Latency Ethernet MAC and PCS is the ideal core for latency critical applications. These IP cores are designed to minimize congestion, to eliminate high fan-out nets, and to ...

450
SDIO/SD Memory/MMC Slave Controller

The SDIO/SD Memory/MMC Slave Controller IP Core supports both 1 and 4 bit SD interface (up to 8 bits in optional MMC support) and SPI mode. Data rate of up to 25Mbyte/sec (200Mbs) can be realized ...

451
SATA Host controller on Virtex 5 FXT

The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is compliant with Serial ATA II specification ...

452
ISO/IEC 14443 type A protocol manager for Proximity Integrated Circuit Card (PICC)

The ISO 14443 Type A Digital Controller is a fully integrated protocol manager intended for Proximity Integrated Circuit Card (PICC).

453
Very High Performance Embedded Microcontroller with Dual Issue Pipeline

The APS29 from Cortus provides a solution to your performance challenges while staying within stringent power and silicon footprint budgets. A dual issue pipeline gives performance close to ...

454
DFI LPDDR5 IP

DFI LPDDR5 is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5 JESD209-5 specification and DFI-version 5.0 Compliant. Through its DFI LPDDR5 compatibility,it provides ...

455
Ethernet 10/40G MAC

The 10 Gigabit Ethernet MAC IP is designed for use in 10 and 40 Gigabit Ethernet applications. For ease of integration into a wide range of applications, this IP is integrated with a 64-bit ...

456
POS-PHY Level 4

The packet over SONET/SDH PHY (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet ...

457
FFT Processor for Microsemi FPGA

Fast Fourier Transform (FFT) Filter Generator CoreFFT v6.4 makes use of multiply-accumulate blocks embedded on-chip in Microsemi's PolarFire, SmartFusion2, IGLOO2 and RTG4 FPGA devices to ...

458
SerialLite II

The SerialLite II MegaCore® function provides a simple and lightweight way to move data from one point to another reliably, at high speeds. It consists of a serial link of up to 16 bonded ...

459
DDR1 DDR2 SDRAM Memory Controller

Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth. Single data rate devices are being replaced by double (and more) data rate devices in applications where memory ...

460
SATA Host Controller

HCLSATAHC26113G core handles data movement between system memory and a SATA device. The core implements transport layer & link layer functions. HCLSATAHC26113G is fully compliant with SATA ...

461
XPS Delta-Sigma Analog to Digital Converter

The analog to digital conversion is realized in the XPS Delta-Sigma ADC (XPS ADC) using Delta-Sigma conversion technique. This soft IP core is designed to interface with the PLB (Processor Local ...

462
XPS External Peripheral Controller

This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC). The controller supports data transfers between the Processor Local Bus (PLB) ...

463
XPS Interrupt Controller

The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. The registers for checking, enabling ...

464
XPS System Monitor/Analog Digital Converter

The XPS SYSMON ADC IP Core is a 32-bit slave peripheral that connects to the PLB (Processor Local Bus) and provides the controller interface for System Monitor (SYSMON) hard macro on Virtex®-5. ...

465
XPS Watchdog Timer

The XPS Timebase Watchdog Timer Interface is a 32-bit peripheral that connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer.

466
XPS Timer/Counter

The XPS Timer/Counter is a 32-bit timer module that attaches to the PLB bus.

467
XPS TFT

The XPS Thin Film Transistor (TFT) controller is a hardware display controller IP core capable of displaying 256k colors. The XPS TFT controller connects as a master on the PLB V4.6 (Processor ...

468
XPS LocalLink FIFO

This core allows memory mapped access to a LocalLink interface. The core can be used to interface to the XPS_LL_TEMAC without the need to use DMA. Other uses include interfacing to the LocalLink ...

469
XPS Mutex

In a multi processor environment the processors share common resources. The mutex provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource. ...

470
XPS PS2 Controller

The XPS PS2 Controller is a PLB (Processor Local Bus) slave that is designed to control PS2 devices such as keyboard and mouse. The PS2 protocol is a simple bidirectional serial protocol.

471
3GPP KASUMI f8 and f9 cores

KASUMI is a 64-bit block cipher which uses a 128-bit key. It forms the basis of the confidentiality (f8 or UEA1) and integrity (f9 or UIA1) algorithms which provide data security for signalling ...

472
Avalon Mobile DDR Memory Controller

The Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in Avalon® multi-master streaming data systems. Advanced design ...

473
SATA-III Host Controller

The so_ip_sata3_hctrl is a soft core implementation of SATA host controller as defined in the SATA Specification 3.2. So-Logic's SATA-III Host Controller core is fully compliant with the ...

474
PCI Master/Target with FIFO and AHB extensions

CorePCIF expands on the popular CorePCI by adding a FIFO interface. PCI is a complex interface with a wide variety of uses in computer and embedded systems applications. CorePCIF and CorePCI ...

475
Soft SDRAM Controller for AXI Interface

CoreSDR_AXI is intended to provide a 64-bit advanced microcontroller bus architecture (AMBA®) advanced extensible interface (AXI) to an external single data rate (SDR) synchronous dynamic random ...

476
USB 3.1 SuperSpeed Device Controller (USB-IF Certified)

Corigine provides USB 2.0, USB 3.0, USB 3.1 Gen 1, and USB 3.1 Gen 2 controllers that are USB-IF certified, which few suppliers can claim. Corigine's SuperSpeed 3.1 USB IP is based on the USB ...

477
USB 3.1 SuperSpeed+ (Gen2) Device Controller (USB-IF Certified)

Corigine provides USB 2.0, USB 3.0, USB 3.1 Gen 1, and USB 3.1 Gen 2 controllers that are USB-IF certified, which few suppliers can claim. Corigine's SuperSpeed and Superspeed+ 3.1 USB IP is ...

478
USB 3.1 SuperSpeed Dual-Role Device Controller (USB-IF Certified)

Corigine provides USB 2.0, USB 3.0, USB 3.1 Gen 1, and USB 3.1 Gen 2 controllers that are USB-IF certified, which few suppliers can claim. Corigine's SuperSpeed 3.1 USB IP is based on the USB ...

479
Super Speed USB 3.0 Extensible Host Controller xHCI

Complies with USB 3.0 Standard for Super Speed (5 Gbps), High Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps). ; Complies with Intel xHCI specification for USB (revision 0.9). ; ...

480

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