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Jacquard jersey fabric IP Listing

565 IP Cores (1 - 40)

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AHB MultiMatrix Fabric

The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configuration support 4 AHB Masters and 7 AHB Slaves ...

1
AXI Fabric Package for Scalable SoC Applications

AndeShape AE300 package in this document refers to two licensable Andes platform products, the AE300FB AXI fabric and the AE300EP example platform. The AE300FB AXI fabric package includes AXI ...

2
CMOS Low Power Programmable Frequency Divider(50-2400 MHz) IP Fabricated

1. 5 to 10 Bit dividing facility. ; 2. Ease of customization and fast deliverable IP as per customers need ; 3. Decoder for selecting same input and output. ; 4. Available in both categories ...

3
AXI Interconnect Fabric

The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5 channels (write address, read address, ...

4
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x000D_

FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, ...

5
AXI bus fabric (AXI Master and Slaves)

CoreAXI supports up to four AXI master interfaces and 16 AXI slave interfaces. The number of AXI master and slaves to be connected is programmable through parameter configuration.The AXI protocol ...

6
Config of FDDR, SERDES; incl Fabric Master Mode

CoreSF2Config facilitates the configuration of peripheral blocks in a SmartFusion®2 device, including the microcontroller subsystem (MSS) double data rate (DDR) controller, known as the MDDR, ...

7
Manage SF2 Reset and sync; incl Fabric Master Mode

CoreSF2Reset handles sequencing of reset signals in a SmartFusion2 device. This core deals with the resets related to the peripheral blocks including the microcontroller subsystem double data ...

8
AHB I/F for Fabric Ram Block

The CoreAHBLSRAM provides access to the embedded large SRAM (LSRAM)and small SRAM (uSRAM) blocks present on SmartFusion2 SOC FPGA family devices through AHB-Lite slave interface. It facilitates ...

9
APB I/F for Fabric Ram Block

The CoreAPBLSRAM provides access to the embedded large SRAM blocks present on SmartFusion2 family devices through APB slave interface. It will facilitate convenient access to Fabric SRAM by ...

10
AHB Subsystem

The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus interfaces such as the BA22-DE, BA22-CE, ...

11
AXI Subsystem

The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces such as the BA20, BA21, and several RISC-V ...

12
AHB Multilayer Interconnect

The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fabric offers higher interconnect throughput ...

13
AXI Multilayer Interconnect

The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric offers high interconnect throughput, as ...

14
100 dB of SNR, 24-bit stereo audio CODEC with headphone driver and digital mixer

Amidst a rich a-la-carte offering, shCODlp-100.02 is an optimized and complete configuration around high performance DAC and ADC cores which provide a higher SNR for the smallest silicon area. ...

15
RSA Public Key Cryptography Exponentiation Accelerator

The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem. It performs the Ae mod M calculation and therefore offloads the most ...

16
I2C Master Controller w/FIFO (APB Bus)

The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C ...

17
8-Bit Microcontroller Core

The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member. WDC's high volume production proven 65xx brand microprocessor family ...

18
8/16–bit Microcontroller

The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member. WDC's high volume production proven 65xx brand microprocessor family ...

19
Accumulator

The Accumulator IP provides LUT and single DSP48 slice accumulation implementations. The Accumulator module can implement adder-based, subtracter-based, and dynamically configurable adder/subtracter-based ...

20
Physical Layer Interface Core

Fully Compliant with Rapid Interconnect Specification Rev 1.1, 3/2001 prescribed by Rapid Trade Association. ; 32-bit standard Host/Link Interface. ; Full Duplex Independent Transmit and Receive ...

21
Register, Configuration and Control Bus

A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc.. The bus is especially suited for synthesizable ...

22
I2C Master/Slave Interface

CoreI2C provides an APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. ...

23
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core

TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY. TRC3002CSA uses double data rate (DDR) transmission for send and receive ...

24
Quad 1 to 2.1Gb/s FC Transceiver

TRC2104SFA is a Quad SERDES for fiber channel applications. It can communicate at 1Gb/s to 2.1Gb/s. It has a low jitter clock synthesizer, 8bit/10bit converter, differential high speed serial ...

25
10Gbps XAUI Transceiver

TRC3114 is a Quad SerDes used as four independent 3.125Gb/s FC, BP, or cable transceiver or 10Gbps XAUI Transceive. It operates with a single 1.8V supply. It has built-in 8bit/10bit converter, ...

26
Core generator for finite impulse response filters

CoreFIR is a core generator for finite impulse response (FIR) filters. The core generator uses a distributed arithmetic implementation methodology to create FPGA-based digital filters. The ...

27
Adder/Subtracter

The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable ...

28
Binary Counter

The Xilinx LogiCORE™ Binary Counter IP core provides LUT and single DSP48 slice implementations. The Binary Counter is used to created up counters, down counters, and up/down counters with ...

29
FFT Processor for Microsemi FPGA

Fast Fourier Transform (FFT) Filter Generator CoreFFT v6.4 makes use of multiply-accumulate blocks embedded on-chip in Microsemi's PolarFire, SmartFusion2, IGLOO2 and RTG4 FPGA devices to ...

30
CoreMP7

Microsemi's CoreMP7 is a soft IP version of the popular ARM7TDMI-S™ that has been optimized to maximize speed and minimize size in Microsemi's Flash-based FPGAs. CoreMP7 ...

31
Divider

The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division. The integer division can be implemented using Radix-2 non-restoring division, ...

32
APB bus to Fusion analog interface

CoreAI (Analog Interface) allows for easy control of the on-chip analog hardware peripherals within the Fusion family of Microsemi devices. Control may be implemented with an internal ...

33
ARM 32-bit FPGA Optimized Processor

Developed by ARM in collaboration with Actel, the 32-bit ARM Cortex-M1 processor is the first ARM processor designed for FPGA implementation. With a balance between size and speed, the free ...

34
CPRI

The LogiCORE™ CPRI IP core is a high-performance IP solution that implements the Common Public Radio Interface (CPRI). The IP core uses industry leading transceivers to implement the CPRI ...

35
AMBA AHB Bus Interface

CoreAHB is an AMBA bus interface that is used to connect subsystem cores to Microsemi's 32-bit soft processors. The bus interface is easy to use and fully compatible with the AHB protocol. ...

36
AMBA AHB-Lite Bus Interface

CoreAHBLite is a multi-master implementation of the AHB-Lite bus interconnect (a subset of the AMBA advanced high-performance bus) used to connect subsystem cores to Microsemi's 32-bit ARM processors. ...

37
AMBA APB Bus Interface

CoreAPB is an AMBA bus interface that is used to connect subsystem cores to Microsemi's soft processors. The bus interface is easy to use and fully compatible with the APB protocol. The core ...

38
AMBA APB 3.0 Bus Interface

CoreAPB3 is an AMBA bus interface that is used to connect subsystem cores to Microsemi's soft processors. The bus interface is easy to use and fully compatible with the APB v3.0 protocol. The ...

39
GPON ONT SERDES (90nm UMC)

PSI2488-U9 is a GPON ONT SERDES capable of receiving serial data at the rate of 2.488Gbps and transmitting data at the rate of 1.244Gbps. The transmitter serializes 8 bit parallel data to a ...

40

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