DesignWare® ARC® EM Safety Island IP are dual-core lockstep processors that simplify development of safety-critical applications and accelerate ISO 26262 certification of automotive system-on-chips (SoCs). ASIL D ready EM4SI and EM5DSI are safety islands based on the EM4 or EM5D processor cores with a pre-verified dual lockstep implementation including a self-checking safety monitor. There is also an option to run the cores in an independent dual core mode for ASIL B or non-automotive applications requiring higher performance based on the same design.
As is the case with ARC cores in general, a tightly coupled architecture is supported such that the interrupt controller, the watchdog timer and options such as μDMA and MPU are tightly coupled to the core; therefore, they are instantiated in the main and shadow core for full redundancy.
The ARC EM Safety Islands are supported by comprehensive safety documentation including FMEDA reports and the MetaWare Toolkit for Safety with ASIL D ready certified compiler to generate ISO 26262 compliant code.
- Dual lockstep safety island supports ISO 26262 automotive safety standards
- Automotive Safety Integrity Level D (ASIL D) hardware, verification and documentation
- Includes hardware safety features: ECC, integrated user-programmable watchdog timer, and lockstep safety monitor
- Supports both ASIL D lockstep operation or ASIL B independent dual-core mode operation
- Performance and area-efficient cores with up to 1.81 DMIPS/MHz and 360 DMIPS/mm2
- Support for DSP instructions and MAC (EM5DSI)
- MetaWare Toolkit for Safety with ASIL D Ready certified compiler
- Extensive safety documentation eases SoC certification process
- ARCv2 ISA Programmers Reference Manual
- ARC EM Databook
- ARC EM Integration Guide
- ARC EM Safety Manual