The DesignWare® ARC® HS34 Processor is a member of the high-speed 32-bit HS Processor Family, optimized for use in high-end embedded applications where real-time, deterministic response is desired. The HS34 Processor can be configured as a dual- or quad-core for applications requiring multicore performance.
The HS34 Processor is based on the highly-efficient ARCv2 instruction set architecture (ISA), delivering a high degree of performance and code density with minimal power and area. These ARC processors are ideal for a variety of high-end embedded applications including SSD controllers, baseband control, digital TV, home networking, automotive systems, smart appliances, and many others.
Like all ARC processors, ARC HS34 Processors are highly configurable, enabling designers to tailor each instance on an SoC for the optimum balance of performance, power and area. The processors can be further optimized with user-defined instructions that enable the integration of a user’s proprietary hardware accelerators to dramatically improve application-specific performance while reducing power consumption.
To minimize system-level latency and increase overall system performance, the HS34 Processor supports close coupled memories and direct mapping of peripherals, providing single-cycle access to other IP and memory blocks on the SoC. Native ARM® AMBA® AXI™ and AHB™ standard interfaces are configurable for 32-bit or 64-bit transactions to optimize throughput.
The HS34 Processors are supported by a robust ecosystem of software and hardware development tools, including the MetaWare compiler/debugger, the nSIM instruction set simulator, the MQX real-time operating system (RTOS), and third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.
- High degree of configurability
- Support for custom instructions
- Support for close coupling of memory and direct-mapped peripherals
- Dual-core and quad-core versions for higher performance
- The DesignWare ARC HS34 Processor is delivered as Verilog HDL in the ARChitect IP Library
- The HDL is configured and output from the ARChitect IP Configurator tool
- 32-bit processor optimized for high-performance embedded applications
- Delivers up to 3100 DMIPS and 5580 CoreMark at 1.61 GHz on 28HPM (worst case conditions)
- 1.93 DMIPS/MHz, 3.47 CoreMark/MHz* (per core) . Based on advanced ARCv2 ISA
- To test that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is included