ARC HS46FS and HS47DFS Functional Safety Processors
Within the processors the interrupt controller, watchdog timer, and options such as cluster DMA and FPU are tightly coupled to the core and are instantiated within the main and shadow core for full redundancy.
The ARC HS Functional Safety processors are supported with comprehensive safety documentation including FMEDA reports and the ARC MetaWare Toolkit for Safety with ASIL D Ready certified compiler to generate ISO 26262 compliant code.
Features
- High-speed, dual-issue, 10-stage pipeline
- Up to 16 MB instruction and data close coupled memory (CCM)
- 4 KB to 64 KB L1 instruction and data cache
- 64-bit loads and stores
- Register file supports 2 write ports and 2 read ports, and up to 8 contexts
- 32x32 multiplier
- Up to 240 interrupts, with up to 16 configurable preemption levels
- Native Arm® AMBA® AXI™ interface
- JTAG and Compact JTAG (cJTAG) debug interface
Benefits
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
- Dual-issue, 32-bit processor for highperformance applications
- Support for DSP instructions
- MetaWare Toolkit for Safety with ASIL D Ready certified compiler • Extensive safety documentation eases SoC certification process
Applications
- ADAS
- Radar
- LiDAR
- V2V, V2x networks
- Vision controllers
- Automotive storage
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