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First interconnect solution specifically for artificial Intelligence applications
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Capless LDO with Noise Quencher Technology (UMC 180 nm, 300 mA, excellent supply rejection and fast settling)
The Capless LDO IP core is optimized for Application Specific Integrated Circuits (ASICs), System-on-a-Chip (SOC) and microprocessor integration. The Capless LDO can hold a steady output voltage reference without using an external capacitor. The LDO uses Noise Quencher(TM) Technology to provide unparalleled power supply rejection at high frequencies.
Benefits
- Adds value to your microchip with embedded power management
- Fewer components and smaller board area (NO external capacitor)
- Improved reliability
- Reduced inventory and reduced BOM management overhead
- Longer battery life (save power through integration)
- Low risk for customer product/program with a silicon proven capless LDO IP core.
Deliverables
- Datasheet and user’s guide with integration guidelines
- Behavioral simulation model
- Schematics and/or spice netlist
- Layout (GDSII)
- Integration and test support
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Capless
- LDO Capless Fast Response Series ( Vin = 1.65-1-95V; Vo = 0-75-1.0V; Io = 150 mA ) - TSMC 28nm
- Capless 1.8V output LDO with 2.0-3.6V input range - SMIC 0.18 EF
- 100 dB of SNR, 16-24-bit stereo audio CODEC with embedded regulator and cap-less headphone driver, including low-power mode
- LDO Capless Fast Response Series ( Vin = 3.0-3.6V; Vo = 1.05-1.15V; Io = 10mA ) - Toshiba 40nm
- LDO Capless Fast Response Series ( Vin = 2.4-5.75V; Vo = 0.9-1.5V; Io = 30mA ) - UMC 130nm
- LDO Capless Fast Response Series ( Vin = 2.3-3.6V; Vo = 2.2-2.8V; Io = 50mA ) - TSMC 65nm