The DesignWare® CCIX Controller IP implements the port logic required to build a root port or endpoint device. The configurable and scalable IP is compliant with the latest CCIX specification, and supports all required features of the PCI Express 4.0, 3.1, 2.1, and 1.1 and PHY Interface for PCI Express (PIPE) specifications. The IP supports cache coherency as defined by the CCIX standard allowing processors and accelerators to use shared memory faster. The high-quality, synthesizable IP is available in your choice of datapath widths, PIPE interface widths, operating frequencies, and over 1200 configuration parameters all working together to enable designers to optimize their applications for size, power, latency and throughput. The DesignWare CCIX Controller IP integrates quickly and easily into system-on-chip (SoC) designs with Synopsys’ native application interface or an industry standard AMBA interface, and provides attainable timing closure in modern silicon processes.
The DesignWare CCIX Controller IP is built upon the successful DesignWare IP for PCI Express which has been silicon validated in over 1500 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market.
- Supports all required features of the CCIX transport specification plus extended speed mode (ESM) at 20GT/s and 25GT/s with targeted process ports at 16-nm and smaller
- Supports all required features of the PCIe 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
- Choice of datapath widths (128- bit, 256-bit, or 512-bit)
- Supports cache-coherency as defined by the CCIX standard
- Synopsys Native Interface with extensions for CCIX, or the optional ARM® AMBA® 4 AXI, or AMBA 3 AXI application interface with extensions for CCIX
- User-optimized configuration to meet latency, area, and power requirements
- The coreConsultant utility to guide designers through the installation, architectural exploration, configuration, verification, and implementation of the IP
- Verilog RTL code
- Example PHY interfaces
- ASIC and FPGA synthesis scripts