The USB 3.0 Hub controller IP Core is a highly configurable core and implements the USB 3.0 Hub functionality that can be interfaced with third party USB 3.0 PHY’s. USB3.0 Hub controller core is part of USB3.0 family of cores named “Pravega”.
The USB 3.0 Hub controller IP Core can be configured to support upto 15 downstream ports.
The USB 3.0 Hub controller IP Core supports all defined USB 3.0 power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.0 PHY for aggressive power savings required for bus powered hubs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
- Compliant with USB3.0 Specification Version 1.0
- Configurable number of downstream ports
- Configurable Core Frequency
- Configurable Internal datapath width: 32, 64, or 128 bits
- Compliant with standard USB 3.0 PHY Interface
- Configurable PHY Interface width: 8, 16, or 32 bits
- Efficient buffering scheme for forwarding packets through hub with minimal latency
- Supports Bus and Self Powered Hub implementations
- USB 3.0 low power states support
- Extensive clock tree gating and multiple power well support for aggressive power savings
- Support for various Hardware and Software Configurability regarding Core characteristics
- Register Interface for internal Register Access
- Optional support for Compound Device Support
- Optional Support for USB2.0 Hub controller
- Synthesizable Verilog RTL
- Configurable System Verilog Verification IP.
- Synthesis Scripts
Block Diagram of the USB 3.0 Hub controller