Comcores Physical Coding Sublayer (PCS) IP core for CPRI 7.0 is a silicon agnostic implementation of the PCS layer described in IEEE Ethernet standard IEEE 802.3 - 2012 and default conﬁgured to meet the requirements of CPRI 7.0. The PCS IP-core enables transmission and reception of data via SerDes interfaces. It is designed to enable easy upgrade of CPRI 5.0 or older version to run with the highest line-speeds.
The core can be dynamically conﬁgured to enable either 8B/10B or 64B/66B encoding/decoding and includes full RS-FEC functionality
To ensure easy integration build-in test capabilities are provided in the core.
- Delivering Performance:
- Complies with CPRI Speciﬁcation V6.1 and V7.0
- Signals can either be 8B/10B or 64B/66B enc/dec
- 64B/66B bus width is fully conﬁgurable from 10-66 bit
- Serdes data bus width can be conﬁgured from 10-40 bits
- Loop back test functionality implemented in core
- Easy to use:
- Very easy integration with AMBA interfaces
- Build-in test capabilities
- Silicon Agnostic:
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
- The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.
- CPRI IP designs:
- A proven interface for upgrading old CPRI controllers
- Used with designs where customer has own proprietary CPRI
Block Diagram of the CPRI PCS IP Core