Optimize DDR Subsystem Efficiency, Power, and Cost
DesignWare DDR Explorer is a performance analysis tool used to optimize DDR subsystem configurations and register settings to find the best results, increase efficiency by up to 20%, and enable the right memory type to be selected for lowest cost and power.
DDR Explorer combines a highly configurable TLM architecture model of the DesignWare Enhanced Universal DDR Memory Controller (uMCTL2) IP with tooling for rapid configuration, simulation, and analysis. Compared to traditional RTL simulation methods, DDR Explorer provides 10x faster simulation turnaround time and deeper visibility into the transaction paths and resources of the DDR memory controller and PHY subsystem.
Using DDR Explorer, designers can increase the efficiency of their DDR memory subsystem configuration to closely match the needs of their application.
DDR Explorer simulations are approximately timed, providing the accuracy needed to analyze performance trends, compare results for different options, and make tradeoffs to optimize your design. RTL simulation is still an important step and is required for validation of your final DDR subsystem configuration. DDR Explorer enables RTL simulation by exporting the chosen configuration in coreConsultant format.
- Advantages for your flow: 10x faster turn-around time; Highly configurable, with deep analysis visibility; Optimize configuration settings as traffic requirements change; Links easily to your existing uMCTL2 RTL flow for validation
- Key features include: Address mapping optimization; Clock frequency optimization; Quality of service optimization; Root cause and sensitivity analysis; Support for mDDR, DDR2, DDR3,DDR4, LPDDR2, and LPDDR3; memory types; Support for coreConsultant configuration, register, and trace files
- Benefits for your design: Increase DDR memory subsystem efficiency by up to 20%; Quickly select the right memory type for lowest cost and power; Achieve system performance for all ports without starvation
- Executable .run installation file
- Databook (PDF)
- Release notes (PDF)
- coreConsultant/coreAssembler tools to generate RTL