DDR4 is full-featured, easy-to-use, synthesizable design, compatible with DDR4 JESD79-4B specification and DFI-version 5.0 Compliant. Through its DDR4 compatibility,it provides a simple interface to a wide range of low-cost devices. DDR4 IIP is proven in FPGA environment.The host interface of the DDR4 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
DDR4 IIP is supported natively in Verilog and VHDL
- Compliant with DDR4 protocol standard JESD79-4B specification.
- Supports up to 16GB device density.
- Supports X4,X8 and X16 devices.
- Supports all speed grades as per specification.
- Supports Mode Registers programming.
- Supports Programmable Write latency and Read latency.
- Supports Programmable burst length of 4 and 8.
- Supports the following burst types,
- Supports Data Mask and Data Bus Inversion (DBI).
- Supports Fine Granularity Refresh Mode.
- Supports Connectivity test mode.
- Supports CRC for Data.
- Supports Command Address Parity features.
- Supports both Synchronous and Asynchronous On-Die Termination modes.
- Supports Power Down features and Maximum Power Saving mode.
- Supports input clock stop and frequency change.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to Microprocessor/Microcontroller devices.
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The DDR4 interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
Block Diagram of the DDR4 Controller IP Core