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ARC EM SEP 32-bit processor core, ARC V2 ISA, for embedded automotive safety applications
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DDR4/DDR3 Memory Controller
The Cadence Denali Controller IP for DDR4/DDR3 is highly configurable DDR IP design, with the ability to optimize bandwidth and latency for high-speed DDR4 applications.
The controller can support legacy DRAM: DRAM: DDR3, DDR2, DDR1, LPDDR3, LPDDR2, LPDDR1, DDR3UL, DDR3L, DDR2L and Everspin DDR3 ST-MRAM.
Advanced low-power option includes automatic power level stepping based on traffic, and hardware-assisted Dynamic Frequency Scaling (DFS), which can be combined on the chipsets for smartphone and tablet applications.
The controller can support legacy DRAM: DRAM: DDR3, DDR2, DDR1, LPDDR3, LPDDR2, LPDDR1, DDR3UL, DDR3L, DDR2L and Everspin DDR3 ST-MRAM.
Advanced low-power option includes automatic power level stepping based on traffic, and hardware-assisted Dynamic Frequency Scaling (DFS), which can be combined on the chipsets for smartphone and tablet applications.
Features
- Compliant to LPDDR 4/3 and DDR 4/3/3L protocol memories
- Single and multi-port host interface options
- Flexible paging policy including auto-precharge-per-command
- Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc
- Priority-per command on ARM(R) AMBA(R)3 AXI and low latency Denali interface
- QoS features allow command prioritization on ARM AMBA4 AXI interfaces
- Silicon proven and shipping in volume
Benefits
- Configurable to meet specific data traffic profiles
- Optimized low latency for data-intensive applications
- Future-proof system design for emerging DDR standards
Deliverables
- Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Documentation: integration and user guide, release notes
- Sample Verification testbench with integrated BFM and monitors
Applications
- Mobile
- Consumer
- IoT
- Automotive
View DDR4/DDR3 Memory Controller full description to...
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