The Double Data Rate 4 (DDR4) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The DDR4 SDRAM Controller core accepts commands using a simple local interface and translates them to the command sequences required by DDR4 SDRAM devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
The DDR4 SDRAM Controller core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core supports all new DDR4 features, including: write CRC, data bus inversion (DBI), fine granularity refresh, additive latency, per-DRAM addressability, and temperature controlled refresh.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY.
- Maximizes bus efficiency via LookAhead command processing, Bank Management, Auto-Precharge and Additive Latency support
- Minimal latency achieved via parameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports half-rate and quarterrate clock operation
- Full run-time configurable timing parameters and memory settings
- Supports all DDR4 operating modes
- DFI 3.0 Compatible including full PHY training support
- Full set of Add-On Cores available
- Delivered fully integrated and verified with target DDR PHY
- RDIMM and LRDIMM support
- Minimal ASIC gate count
- Broad range of ASIC and FPGA platforms supported
- Source code available
- Customization and Integration services available
- Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates
Block Diagram of the DDR4 SDRAM Controller IP Core