Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 6.5Gb/s per lane and 6.5Gs/s per trio respectively for a maximum speed of 44.5Gb/s. DesignWare C-PHY/D-PHY addresses energy requirements by supporting low-power state modes and delivering below 1.2pJ/bit at the maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes. The DesignWare C-PHY/D-PHY IP interoperates with Synopsys CSI-2 controller which supports key features of the latest MIPI camera specification.