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DDR5/4 PHY for TSMC 16FFC
The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 4800 Mbps. The DesignWare DDR5/4 PHY is ideal for systems that require highspeed DDR5/4 performance and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/ Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/ Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with Synopsys’ DDR5/4 controller for a complete DDR interface solution.
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SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.