Synopsys' silicon-proven DesignWare® MIPI® M-PHY IP is compliant with the latest MIPI Alliance M-PHY v4.1 specification and supports a wide range of high-speed interfaces for mobile applications including JEDEC Universal Flash Storage (UFS), and MIPI UniPro and Low Latency Interface (LLI) interfaces.
The DesignWare MIPI M-PHY IP supports HS Gear1, Gear2, Gear3, and Gear4 rates ranging from 1.248 Gbps to 11.6 Gbps. Low-speed capabilities are available via Type-1 M-PORTS with Gear1 to Gear5 PWM modes and Type-II M-PORTS, allowing for SYS-BURST mode. The M-PHY’s modular architecture allows implementation of a variety of transmitter and receiver lanes to meet a broad range of applications and all the modes outlined in the protocol specification. A sophisticated clock recovery mechanism and power efficient clock circuitry are designed to guarantee the integrity of the clocks and signals needed to meet strict timing requirements. The DesignWare MIPI M-PHY IP supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI).
The DesignWare M-PHY IP easily integrates with the DesignWare MIPI UniPro Controller and UFS Host Controller via the RMMI interface to allow a complete interface for mobile storage applications.
Extended Reference clock support: 19.2, 26, 38.4 and 52MHz
Common lane configuration support for mobile IC applications
Fast entering and recovery from/to low-power modes
Optimized EMI performance through the use of slew rate control and dithering
Large and small amplitude
Sophisticated clock recovery mechanism
Power efficient clock circuitry for high-speed and low-speed clock generation
Advanced test features simplifies debug and production test procedures