Multi-Protocol 32G PHY for TSMC N5
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) to reduce design time and to help designers achieve first-pass silicon success.
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PCI Express PHY IP
- 1-32Gbps PCI-Express Gen1 - Gen5 PHY
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support
- Gen5 PCIe Transparent Switch