The END-SYSTEM-IP-2TX1G-E/A664P7 CETRAC End-System IP core is the ideal solution to interconnect any Ethernet and ARINC 664 Part 7 equipment/IP. The CETRAC End-system IP is high performance, safe, real time and deterministic.
The CETRAC END-SYSTEM IP core is fully compliant with Ethernet/A664P7 protocols and allows both cyclic and event-driven communications in full duplex. It embeds the ARINC664 Part 7 redundancy management feature at up to 1Gbps.
The CETRAC SAFE Ethernet END-SYSTEM IP is a pure hardware IP core and has been developed with modularity and scalability as main drivers such that it allows to interface any kind of CPU within a very short TTM.
The END-SYSTEM-IP-2TX1G/E-1588 CETRAC safe Ethernet END-SYSTEM IP core can be instantiated and connected with customer IP within the same FPGA/ASIC to create a dedicated and customized end-system solution.
- Compliant with 802.3 Ethernet standard at 10/100/1000Mbps
- Compliant with 802.3 Ethernet standard at 10Gbps
- Compliant with IEEE1588 standard
- Enabled to IMA2G
- Protocol availability : UDP-IP, SNMP
- Developed according to RTCA/DO-254 ED-80 guidance.
- System clock distribution
- Dual link redundancy
- Guaranteed Real Time and QoS.
- Network topology free
- Security features, fault detection and reporting
- WCET is guaranteed to be within the same timescale as the nominal case time.
- 2 Ethernet ports at 10/100/1000 Mbps
- Dual Ethernet port at 10Gbps is also available
- Scalability and modularity
- Internal clock resolution at 5ns
- Dual link redundancy
- Monitoring function availability
- Data access methods: Queuing, Flip/Flop, sampling or file type mode
- Scheduling transmission : cyclic frames management
- Data integrity feature
- xBIT monitoring
- very short TTM
- The Safe Ethernet END-SYSTEM IP core is a multi-protocol IP compliant with both IEEE802.3 (time sensitive and non critical network) and IEEE1588 standard. The synchronisation with other IP/Device is insured in a standard format to bring and reinforce realtime and deterministic capability.
- Thanks to its segregation architecture, the CetraC IP allows to manage within the same IP deterministic and none-deterministic frames.
- New protocol such as VISTAS can be implemented within the same IP core to reinforce the multi-protocol characteristics
- The CETRAC system interconnection solution provides native full duplex and deterministic communication with best Quality of Service all over the entire network as well as:
- Optimal bandwidth
- High availability providing redundancy management, automatic communication, error detection, transparent error fixing
- The network can be entirely modelled in order to predict the communication worst cases
- Key solution advantages (as well as safety, bandwidth, speed, scalability, architecture flexibility …) will insure use case universality. Targeted applications are:
- Critical Systems such as Control and Command
- Tests beds
- Perfect replacement of complex wiring architecture based on , Sercos, Digibus, FlexRay,…
- The CETRAC Safe Ethernet END-SYSTEM IP core has been designed and manufactured according to the RTCA/DO-254 ED-80 guidelines. This IP product has been developed, verified and licensed by SILKAN.
- Switching and redundancy features are implemented in pure hardware and provides much more performances than SW based solutions.
- Encrypted RTL code compliant with SILKAN’s design standard.
- Reference Design as integration example
- SILKAN’s support includes technical integration, DO-254/26262 integration and certification phases.
- As the CetraC technology is a pure Hardware solution (No CPU, No Software).
- A wide varity of safe and cyber secure platform is possible:
- Critical Systems in Aircraft, Automotive and railway.
- Aerospace System Design requiring DO-254 certification.
- Automotive applications that requires 26262 quality process with high availability such as ADAS, LIDAR.
- Entertainment systems that requires high bandwidth and very low latency.
Block Diagram of the DO254-IP: 1/10Gbps Safe Ethernet / IEEE1588 End-System IP