The DSI Controller Core is designed to achieve maximum MIPI throughput while being easy to use.
The core implements all three layers defined by the DSI Specification: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the DSI specification. Separate Host (Tx) and Peripheral (Rx) versions of the core are provided.
The core’s provides 4 data and 1 control/status packet interfaces. The data interfaces can be optional adapter to DBI or DPI interfaces. The control/status interface can be optionally adapted to an AXI interface. The core supports command and video modes, 1 to 4 data lanes and all data types.
The core uses the byte lane clock minimizing power consumption and ensuring the core can be used in older process technologies.
The core is delivered fully integrated and verified with the user’s target MIPI PHY.
The core is also provided with the MIPI Testbench which provides a MIPI Bus Functional Model.
- Fully DSI-2 standard compliant
- 64 and 32 bit core widths
- Host (Tx) and Peripheral (Rx) versions
- 1-8, 2.5+ Gbit/s D-PHY data lane support
- 1-4, 2.5+ Gsym/s C-PHY lane (trio) support
- Support for all data types
- Easy to use native interface
- Optional DBI & DPI data interface
- Delivered fully integrated and verified with target MIPI PHY
- Provided with a DSI-2 Testbench
- Minimal ASIC gate count
- Source code available
- Customization and Integration services available
- Complete FPGA-based demonstration system available
- Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates