DVB-C/J83 Demodulator IP Core

Features

• EN 300 429 & ITU-T J.83 Annex A/C
• Supports 16, 32, 64, 128 and 256 point constellations
• Supports Standard IF and Low IF
• 10 bit ADC interface
• Symbol rates up to 7M Baud
• Serial or Parallel transport stream outputs
• RF & IF AGC Outputs (PWM Outputs)
• Self-adapt spectrum inversion
• Easy control and monitoring via Two-wire Serial Bus
• Additional private Two-wire Serial Bus dedicated to tuner control for minimum tuner disturbance.

Deliverables

• Synthesizable Verilog / Synthesizable RTL
• System Model
• Reference C-model
• Verilog Test Benches
• Documentation
• FPGA testing / evaluation environment

Block Diagram of the DVB-C/J83 Demodulator IP Core

• see the entire DVB-C and J.83 A/C Demodulator datasheet
• get in contact with DVB-C and J.83 A/C Demodulator Supplier