DVB-S2 defines a "second generation" modulation and channel coding system. DVB-S2 is a single, very flexible standard, covering a variety of applications by satellite. For error correction DVB-S2 standard incorporates LDPC (Low Density Parity Check) coding combined with BCH (Bose-Chaudhuri-Hocquengham) coding. The combination of these two techniques has been proved to provide excellent performance in the presence of high noise levels and interference.
- DVB-S2 Compliant Parallel BCH Encoder. The DVB-S2 requirement uses two Galois fields i.e. and with three values of T.
- Short (16200 bits) and Normal (64800 bits) frame compliant
- The BCH parameters including Galois Field Parameters, block size N and correcting power T, are decoded from a fixed set of modes.
- Data input and output will be multi-bit sequential, MSB first.
- High Speed, High Throughput, Continuous mode Encoding
- Low Encoder latency and High throughput,
- Fully synchronous design with 2-bit input and output data busses
- Technology independent
- The core could be customized as per the customer requirements.
- Design document describing the complete architecture level details
- Complete Verification plan document
- Well commented out high quality Synthesizable Verilog HDL source code
- Complete verification environment with automated test bench
- Complete suite of test vectors for verification
- Source code in VHDL could also be provided on request
- Simulation script, vectors and expected results
- The core is available in FPGA (Netlist) forms, and includes everything required for successful implementation.
- Expert Technical Support and Maintenance Update