- This IP is extracted from a 6th generation high volume production chip, Broadcaster certified globally, and ready for technology transfer.
- Fully compliant and fully featured for DVB S2X/S2/S, T2/T, C standards and specifications, exceeding the standard to deliver superior performance and meet Broadcaster requirements.
- The IP implements high-symbol– rate (HSR) demodulators compliant with Annex M of the DVB-S2X/S2 specification EN 302 307, and provides full HW support for network clock recovery (NCR) in order to enable external return-channel modulators. It also has been designed to enable single – carrier usage of HTS transponders.
- It is a soft core, completely self contained, with no 3rd party IP (CPU, DSP)
- Compatible with zero -, high – and legacy – IF tuners (CAN or silicon
- Can be customized to meet specific features or requirements
- Has been licenced numerous times
- Source Code delivery for full technology transfer.
- Extracted from 6th generation high volume production chip
- Full DVB S2X/S2/S, T2/T, C compliant
- Multiple Broadcaster certified
- Compliant with ETSI EN 302 307-1 V1.4.1 (2014-11) (DVB-S2) and ETSI EN 302 307-2 V1.1.1 (2014-10) (DVB-S2X).
- Supports CCM, ACM and VCM modes.
- Support for QPSK up to 256-APSK.
- DiSEqC 1.x and DiSEqC 2.x compatible
- Support for short blocks (16200 bits) and long blocks (64800 bits).
- Source Code Delivery
- Technical Documents
- Verilog Source RTL Code plus Simulation Environment
- C Source Code Physical Design scripts - Synopsys synthesis
- Hardware simulation test bench with regression test suit
- Reference platform drivers