The EFLX™-2.5K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up- Tables (LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 20Kbits RAM, an improved interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. Gen 2 improvements reduce LUTs required by 20-30% and improve critical path performance by ~25% for typical RTL.
The EFLX-2.5K DSP core has 40 DSP MACs (22x22 multiplier with 48 bit accumulator). In the Gen2 architecture, MACs cascade up to 10 stages without using the interconnect network. Each EFLX core is a standalone embedded FPGA. Cores can be arrayed up to 7x7 to create arrays of >100K LUTs. Logic and DSP cores can be mixed. And RAM can be integrated as well.
Our improved, Gen 2 programmable interconnect has been optimized for higher performance, especially for large arrays. Metal utilization is just 6 layers of routing metal and is compatible with almost all metal stacks.
EFLX features full connectivity inside the core, and provides additional interconnects at the boundary to concatenate multiple cores via the expandable network I/Os: ~50 array sizes are possible from 2,500 LUTs up to 122,500 LUTs.
Gen 2 DFT improvements achieve >98% coverage of all faults (higher with larger test vectors) & a new configuration load mode for test reduces test times about 100 times faster than Gen 1 to lower test costs.
The EFLX-2.5K Core has 632 user inputs and 632 user output pins placed as follows: 64 West, 64 East, 252 North, and 252 South. The I/O pins provide user access to the EFLX core. Each I/O has a bypassable flip flop. When multiple cores are concatenated into EFLX arrays, the user I/Os along the abutting edges are disabled (or are used for controlling embedded RAM blocks).
Besides user I/O, there are clock, configuration, and test/DFT pins. Each Core has an internal power grid which can be connected to the customer’s digital SoC power grid. The Core has power control pins. The Core also has configuration inputs on the West side and configuration inputs on the South side to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connect points.
EFLX in 16nm is very dense: the density in LUTs/square mm is similar to the Intel® Stratix® 14nm FPGA described at ISSCC 2017.
Readback circuitry in Gen 2 enables configuration bits to be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications. A new test mode enables test times about 100x faster to lower test costs.
The EFLX-2.5K Logic and DSP cores will be proven in silicon by a validation chip that enables testing at >500MHz over temperature and voltage.
To the right is the high level GDS of the validation chip which is being fabricated which includes a 7x7 array of EFLX-2.5K cores (14 EFLX-2.5K DSP cores and 35 EFLX-2.5K Logic cores). The validation chip also includes numerous banks of high speed RAM, PVT monitors and a PLL: all of this is to enable high speed testing at precise Vj and Tj conditions for validation of specifications. An evaluation board will also be available to run actual RTL.
- Front-end Design view (with NDA)
- Encrypted Verilog Model
- Footprint LEF
- Detailed datasheet & DSP User’s Guide
- Silicon validation report
- EFLX Compiler evaluation version
- Back-end Design Views (with License)
- Verilog Model
- CDL/Spice netlist
- Integration guidelines
- Integration assistance as needed
- EFLX Compiler bitstream generation version
- Test vectors