EBR-1553 IP Core - Enhanced Bit Rate
The memory is a true dual port RAM as defined by the FPGA target, with both sides independently reading or writing data. The CPU should supply the memory control signals, address, data, chip select and write enable synchronized with the clock signal supplied to the core. This synchronized approach will ensure robustness of operation. Since the core and the user logic work with the same clock, the design will have no transient effects.
EBR1553D can be used on any FPGA, using any clock frequency and memory size. This ensures quick and reliable integration with user’s design. The parametrically settable clock frequency can be set from 60 Mhz and up – reduces number of clock domains in design.
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Block Diagram of the EBR-1553 IP Core - Enhanced Bit Rate

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