The Enhanced Bit Rate 1553 IP Core is suitable for any Enhanced Bit Rate 1553 implementation. It incorporates decoder/encoder suitable for EBR1553 implementation over RS-485 physical interface. The words received and transmitted are arranged in a dual port memory according to the memory mapping of the DDC® Enhanced mini-ACE®. The CPU controls the EBR1553D by programming the dual port memory for message specific settings, and programming a set of configuration registers for device wide controls.
The memory is a true dual port RAM as defined by the FPGA target, with both sides independently reading or writing data. The CPU should supply the memory control signals, address, data, chip select and write enable synchronized with the clock signal supplied to the core. This synchronized approach will ensure robustness of operation. Since the core and the user logic work with the same clock, the design will have no transient effects.
EBR1553D can be used on any FPGA, using any clock frequency and memory size. This ensures quick and reliable integration with user’s design. The parametrically settable clock frequency can be set from 60 Mhz and up – reduces number of clock domains in design.
- 10 Megabits per Second 1553 protocol Intellectual Property for FPGAs and ASIC
- Suitable for any EBR1553 BC, RT, MT implementation
- Back-end compatible to DDC® Mini-Ace® and Enhanced Mini-Ace® interface and functionality, works with existing software drivers
- Small FPGA area utilization
- Supports any even clock frequency
- Modular architecture allowing flexible implementations
- Provided with full verification environment
- Based on vendor and technology independent VHDL code
Block Diagram of the EBR-1553 IP Core - Enhanced Bit Rate