We offers the High performance,high quality, fully verified and Synthesizable Memory Controllor IP core for GDDR5 SGRAM devices.
Please Note the IP is Controller Only and the PHY is not included.
- Memory controller for GDDR5 memory deivces compliant to JEDEC JESD212C Specification.
- The Memory Controller comes in FPGA and ASIC verisons.
- Sign once IP licence.
- Compatible and Well defined PHY interface.
- Floor-plan,Power,Frequency and P&R aware Design.
- AMBA AXI4 as CPU/DMA Interface.
- AMBA APB as Firmware interface.
- Scheduling and Buffer Management to trade off Command latency vs Bank utilization.
- Firmware programmable timing parameters and GDDR5 Device management.
- Software defined Initialization,Training,Refresh and power management.
- High throughput design exploiting multi-bank array organisation of the GDDR5 devices.
- Effective utilization of Command bus by monitoring device states and scheduling eligible commands during bank access restriction periods.
- Fully Customizable design.
- Freedom to optimize the design for unique implementations that would require the modification of the source on a per-use basis.
- Simple Licencing scheme free of financial, temporal, and contractual overheads.
- Fully compliant to the industry standard.
- Verification sign-off based on exhaustive stimulus with self checking test-bench.
- Source code with well documented Comments.
- Reference Manuals, Integration guide and Debugging Manual.
- free of cost Memory controller wrapper to integrate with PHY.
- pre and post silicon technical support in bring-up and debug.
- Synthesizable RTL design in Verilog with Comments.
- SystemC/Verilog Testbench.
- Synthesis Constraints file.
- Documents for Reference,Integration.
- Graphics Cards.
- Gaming Consoles.
- HPC/Super Computing.
- Coin Mining.
- cryptocurrency systems.
- High Bandwidth Parallel Computing Co-processors.