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GDDR6 and GDDR5X PHY IP
The Six Semiconductor Inc’s GDDR6 PHY IP is designed to be fully compliant to multiple JEDEC standards for GDDR6/GDDR5X support, with maximum data rate up to 16Gbps in GDDR6 mode. With full backward compatibility to the GDDR5X standard, the PHY provides flexible memory options for SOC platforms to optimize for specific price/performance target. The PHY is constructed as a two 16-bit instance, complete with Command Address interface as well as shared PHY components.
The 2x16-bit GDDR6 PHY instance is complete with built-in hardware logic for CA, WCK2CK, Read and Write data eye training, as well as hardware for continuous phase tracking to compensate supply voltage and temperature drift.
The GDDR6 PHY IP is delivered in both Soft-IP and Hard-IP components. The soft-IP component can be hardened upon request. For top/bottom die edge vs left/right die edge PHY instantiations, a different hard-IP view is available and would be required.
The 2x16-bit GDDR6 PHY instance is complete with built-in hardware logic for CA, WCK2CK, Read and Write data eye training, as well as hardware for continuous phase tracking to compensate supply voltage and temperature drift.
The GDDR6 PHY IP is delivered in both Soft-IP and Hard-IP components. The soft-IP component can be hardened upon request. For top/bottom die edge vs left/right die edge PHY instantiations, a different hard-IP view is available and would be required.
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Block Diagram of the GDDR6 and GDDR5X PHY IP
