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GDDR6 and GDDR5X PHY IP
The Six Semiconductor Inc’s GDDR6 PHY IP is designed to be fully compliant to multiple JEDEC standards for GDDR6/GDDR5X support, with maximum data rate up to 16Gbps in GDDR6 mode. With full backward compatibility to the GDDR5X standard, the PHY provides flexible memory options for SOC platforms to optimize for specific price/performance target. The PHY is constructed as a two 16-bit instance, complete with Command Address interface as well as shared PHY components.
The 2x16-bit GDDR6 PHY instance is complete with built-in hardware logic for CA, WCK2CK, Read and Write data eye training, as well as hardware for continuous phase tracking to compensate supply voltage and temperature drift.
The GDDR6 PHY IP is delivered in both Soft-IP and Hard-IP components. The soft-IP component can be hardened upon request. For top/bottom die edge vs left/right die edge PHY instantiations, a different hard-IP view is available and would be required.
The 2x16-bit GDDR6 PHY instance is complete with built-in hardware logic for CA, WCK2CK, Read and Write data eye training, as well as hardware for continuous phase tracking to compensate supply voltage and temperature drift.
The GDDR6 PHY IP is delivered in both Soft-IP and Hard-IP components. The soft-IP component can be hardened upon request. For top/bottom die edge vs left/right die edge PHY instantiations, a different hard-IP view is available and would be required.
Features
- 2x16-bit PHY instance
- Compliant to JEDEC standards: JESD250 (GDDR6), JESD232A (GDDR5X)
- Data rates up to 16Gbps(GDDR6) and 12Gbps(GDDR5X)
- PHY Independent mode training and calibration
- Continuous phase correction
- Supports multiple frequency states with fast switching time
- Memory controller interface based on DFI standard
- JTAG interface for test mode control
- Channel equalization with transmit de-emphasis and receive CTLE/DFE
- Supports both POLY orientations
- ESD compliant to HBM2KV & CDM500V
- Full speed internal and external loopback
- Self-contained PHY testing
- I/O bypass for boundary scan
- Analog and digital observation I/Os
Benefits
- Schematic and layout co-design resulting in smallest and most power efficient PHY
- Max data rates achieved with standard package and PCB materials and design rule
- Designed by team of engineers who has successfully deployed GDDR5 memory interface on multiple generations of world class GPU
Deliverables
- Documentation
- PHY Databook
- Implementation Guideline
- Package and PCB Design Guideline
- Test and Characterization Guideline
- Hard IP Deliverables:
- Behavioral model (Verilog)
- Layout abstract (LEF)
- Timing models (lib/db)
- Layout (GDSII)
- LVS netlist (CDL)
- Physical verification reports
- Soft IP Deliverables:
- Synthesizable RTL (Verilog)
- Synthesis and STA constraints
- Example testbenches
Applications
- Deep learning accelerator
- Datacentre networking switches
- Cryptocurrency ASICs
- Autonomous driving systems
Block Diagram of the GDDR6 and GDDR5X PHY IP
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