The Gen3 PCIe Transparent Switch is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.
The Gen3 PCIe Transparent Switch is part of the PCI-Express (GPEX) family of IP solutions which includes End Point (GPEX-EP), Root Complex (GPEX-RC), Hybrid (GPEX-HY), Switch port Controller (GPEX-SW), GPEX-AXI Bridge (GPEX-AXI), GPEX-AHB Bridge (GPEX-AHB) and Advanced Switching (GPEX-AS) designs.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. The solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
The Gen3 PCIe Transparent Switch leverages years of experience in PCI, PCI-X and HyperTransport technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
- Compliant to PCI Express base specification version 4.x
- Errata for 4.0 and backward compatible with PCI Express versions 3.0, 2.0 and 1
- Architected for high link utilization and low latency
- Non-blocking architecture.
- 32/64/128/256/512 bit Datapath
- Each port can support a unique feature set.
- Completely handles PCI-Express ordering rules
- Implements flow control logic for both directions
- Optional AMBA Master and Slave Interface to the Application logic
- 8bit/16/32-bit Pipe interface for external ports on link side.
- Support for link re-configuration, programmable link width on multi-lane ports
- Supports parallel address decoding at each ingress port
- Advanced Error reporting for all switch ports and embedded endpoints
- Full PCI-PM and ASPM Support for L0s, L1
- Configuration access to internal ports and type-1/type-0 conversion for configuration transactions targeted to downstream devices
- Unsupported request and unexpected completion handling for both upstream and downstream traffic
- Round Robin and Strict Priority arbitration with starvation detection options for Port Arbitration
- Implementation specific registers for external ports and embedded endpoints
- Superior architecture-optimized for high performance, link utilization, low latency, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with leading VIP
- Verilog RTL
- Behavioral test bench and test cases
- PCI Express and Application BFM
- ASIC Synthesis environment
- PC’s workstations and servers
- Networking and communications
- Switches and routers
- General purpose system chip interconnect for any compute platform
Block Diagram of the Gen3 PCIe Transparent Switch