The Trilinear Technologies M4 Digital Video Decoder is a hardware only implementation providing high quality and high performance h.264 video decoding. The M4 core supports the Constrained Baseline and Main Profiles as well as providing optional support for the High4:2:2 profile. All profiles are capable of decoding streams at the 4.2 level for FPGA implementations and the 5.1 level for ASIC implementations.
The host system communicates with the M4 core using the AMBA 3 APB slave interface. Control and status information provides real-time visibility of the core for applications requiring fine control of the decode process. For most applications, the core implements an autonomous mode where decoding proceeds without input from the host until a specified break point is reached.
The frame store is accessed through a direct high speed, wide bus, memory interface. Decoded picture storage can be configured based on the input video stream which allows the minimum amount of memory to be allocated for a specific stream. The memory system is tolerant of high latency which makes the M4 core ideal for implementation in a shared memory system.
The M4 Digital Video Decoder core ships with a complete reference driver and a fully documented API. The core is available on the Trilinear Technologies’ Viper Development platform. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
The M4 core can be delivered as either a technology specific firm core or a technology independent soft core and may be implemented on both FPGA and ASIC platforms. The Trilinear Technologies’ development process allows for the migration of soft cores from FPGA to ASIC for prototyping and production solutions with no core modifications.
- Main and Baseline Profile
- Optional High 4:2:2 Profile
- Decodes up to level 4.2 (FPGA) or 5.1 (ASIC)
- Supports full performance FPGA and ASIC Implementations
- Main Profile Support
- I, P, B-slices
- CAVLC and CABAC Entropy Coding
- In-Loop Deblocking Filter
- Interlaced Coding
- Multiple Reference Frames
- High 4:2:2 Profile Support
- Transform Adaptivity
- Quantization Scaling Matrices
- Separate Cb/Cr QP Control
- 4:2:2 Color Space
- Monochrome Video Format
- Core Details
- Low CPU Overhead
- Designed for a Shared Memory Architecture
- Low core clock rate <250MHz
- Up to 100Mb/sec @ 200MHz
- FPGA Development Platform
- 32-bit MIPS CPU based system
- DVI Video Output
- Downloadable Applications
- CompactFlash Stream Storage
- Hardware Driver and Reference Player Included
- HDL source files for the function design
- HDL source files for block level and top level testing
- Functional specification
- Timing constraints summary document
- Generic SRAM simulation models
- C Reference Driver
- C Video Player Application
Block Diagram of the H.264 HL Digital Video Decoder IP Core