tHE High Bandwidth Memory (HBM) DRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by HBM DRAM devices. The core also performs all initialization and refresh functions.
The core uses bank management modules to monitor the status of each SDRAM bank (up to 64 banks managed concurrently). Banks are only opened or closed when necessary, minimizing access delays. The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core supports all HBM features, including: data bus inversion (DBI), DQ parity, command / address parity modes, and single-bank refresh.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY. Northwest Logic supports a broad range of third party PHYs.
- Supports HBM Gen2 pseudochannel and Gen1 legacy modes
- Supports up to 1.2 GHz HBM operation (2.4 Gbps/pin)
- Dual and single controller options available
- Dual and single user interface options available
- Maximizes bus efficiency via Look- Ahead command processing, Bank Management, and Auto-Precharge
- Minimal latency achieved via parameterized pipelining
- Full run-time configurable timing parameters and memory settings
- DFI 3.1 Compatible (with extensions added for HBM)
- Full set of Add-On Cores available
- Delivered fully integrated and verified with 3rd party ASIC PHY
- Supports all defined HBM channel densities, from 1 Gb to 8 Gb
- Supports HBM Self-Refresh and Power-Down modes
- Customization and Integration services available
- Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates