EnSilica’s eSi-3250 32-bit CPU core is a high-performance processor ideal for integration into ASIC and/or FPGA designs with off-chip memories. The eSi-3250 is suited to a wide range of applications including running complex operating systems such Linux and uClinux.
The processor features separate instruction and data caches that can be configured in size (from 1-64kB) and associativity (direct mapped, 2 or 4-way associative) to increase performance when accessing off-chip memory. The optional paged memory management unit (MMU) enables the implementation of virtual memory and the ability to run operating systems such as Linux.
The 5-stage pipeline allows extremely high clock frequencies to be achieved. While most instructions effectively execute in a single clock cycle, the deep pipeline allows the C and C++ compiler to schedule independent instructions such that instructions that can take multiple cycles to execute, appear to only take 1 clock cycle. Static branch prediction is employed to minimize the cost of branch instructions.
The eSi-3250’s instruction set includes arithmetic and logical instructions (including barrel-shift, multiply and divide), comparisons, load and stores, branches and calls as well as system level instructions to control interrupts and enter lower power states. There are also a number of optional instructions and addressing modes that can be selected, should a specific application require them. For example, an set of IEEE-754 compliant single-precision floating point instructions are available. For those applications that require extreme performance or ultra low power operation, user defined instructions can be implemented.
A number of instructions are reserved to allow the user to utilise user defined logic via a simple interface. User defined registers and condition codes are also supported, allowing the most complicated applications to be accelerated.
Instructions are encoded in either 16 or 32-bits, depending upon the size of the operands and the type of instruction. All of the commonly used instructions can be encoded in 16-bits. This ensures that high code density is achieved, which helps to increase performance by increasing the number of instructions that can be stored in the instruction cache. The processor supports both user and supervisor operating modes, with privileged instructions and memory areas, to allow an O/S kernel to be fully protected from user applications.
For applications that require do not require off-chip memory, the smaller eSi-3200 is available. For even simpler applications that do not require 32-bit performance or more than 64kB of data memory, the eSi-1600 16-bit processor can be used. The eSi-1600 processor features the same ISA as the eSi-3250, reduced to 16-bits. All of the eSi-RISC processors RTL and toolchains share a common code base, resulting in an easy migration path for both software and hardware developers, should the demands of an application change.
The toolchain for the eSi-3250 is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customizable Eclipse IDE (Integrated Development Environment). The debugger can connect to the target CPU either via JTAG or a serial interface. Complete C and C++ libraries are supplied. Ports of FreeRTOS, Micrium uC/OS-II, Contiki and TinyOS are available. The toolchain is available for both Windows and Linux hosts and is available to use at no cost.
EnSilica is a quality provider of ASIC, FPGA and IP design service encompassing wired and wireless systems design, IP selection, low-power design and SoC integration, functional verification and silicon implementation. Application specific acceleration, peripheral design and software and tools development services can be offered to support product development using our range of eSi-RISC IP cores.
- 32-bit RISC architecture
- 32 general purpose registers
- 104 basic instructions and 10 addressing modes
- Optional IEEE 754 floating point unit (FPU)
- Supports up to 96 user-defined instructions
- 5-stage pipeline
- Optional memory management unit (MMU)
- Configurable instruction and data caches (1-64kB. Direct mapped or 2 or 4-way associative)
- AMBA AXI or AHB interconnect and APB peripheral bus
- User and supervisor operating modes
- Up to 32 interrupts plus NMI and system call
- Fast interrupt response time of 6-9 cycles
- JTAG or serial debug
- Delivers 2.71 CoreMark per MHz
- ASIC Performance (Typical 90nm):
- Up to 700MHz
- From 20k gates
- From 22 uW/MHz
- FPGA Performance (Stratix IV):
- Up to 200 MHz
- From 2200 LUTs
- High code density
- Intermixed 16 and 32-bit instructions
- High quality IP:
- C and C++ s/w development using license-free GNU tools, under industry standard Eclipse IDE
- Easy migration path to cacheless implementation
Block Diagram of the High-performance 32-bit Processor with cache IP Core