Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The DesignWare® Duet Package of Embedded Memories and Logic Libraries for GLOBALFOUNDRIES’ 40-nanometer (nm) Low Power (LP) process includes standard cells, SRAMs, register files, ROMs and Power Optimization Kits (POKs) – all the elements needed to implement a complete SoC. Options for overdrive/low voltage PVTs, high density SRAMs, multi-channel cells, and memory built-in self test (BIST) and repair are also available, enabling designers to achieve the best combination of performance, power and area in their designs. DesignWare Embedded Memories and Logic Libraries are extensively proven in silicon with billions of units shipping in volume production, lowering project risk and speeding time-to-market.
The DesignWare Embedded Memory Compilers and Logic Library IP for the GLOBALFOUNDRIES 40LP process provide built-in power management features that enable system-on chip (SoC) designers to explore trade-offs between performance, area, and power to generate optimal memory configurations. This dashboard control capability is critical at 40-nm where design and process complexities require sophisticated management of the various trade-offs to effectively meet stringent end-product requirements and increasingly narrow time-to-market windows.
The high-density memory compilers are optimized to generate memories with the absolute minimum area and power, enabling designers to achieve aggressive, critical path requirements. The high-density memory compilers minimize both static and dynamic power consumption, while the high-speed memory compilers provide a much higher level of performance.
The logic libraries include yield-optimized standard cells for a wide variety of design applications at 40 nm with multiple threshold process variants and multiple channel lengths. The DesignWare Logic Libraries offer two separate architectures of 1,600 cells, each to optimize circuits for high-density or high speed. The included Power Optimization Kits (POKs) provide designers with the most advanced power management capabilities.
- Silicon-proven, shipping in volume production
- Broad portfolio of high-speed, high density and low-power memory compilers and logic libraries
- Largest standard cell library with over 1,400 cells
- Integrated test and repair solution delivers higher test quality and yield, while lowering overall chip areas
- CDL and other industry standard design views