Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. Optimized for UMC’s 28-nm high-performance, low-power (HLP) process technology, the DesignWare® Duet Package of Embedded Memories and Logic Libraries includes standard cells, SRAMs, register files, ROMs, High Performance Core (HPC) Design Kits and Power Optimization Kits (POKs) — all the elements needed to implement a complete system-on-chip. Options for overdrive/low voltage PVTs, ultra high-density memory, multi-channel cells, and memory built-in self test (BIST) and repair are also available, enabling designers of mobile applications that require high speed and low-leakage power to achieve the best combination of performance, power and area in their designs. DesignWare Embedded Memories and Logic Libraries are extensively proven in silicon with billions of units shipping in volume production, lowering project risk and speeding time-to-market.
- Broad portfolio of high-speed, high-density and ultra-high density memory compilers
- Complete standard cell library supporting multiple architectures (10.5T, 9T and 7.5T), VTs, gate biases, PVTs
- High Performance Core (HPC) package of special standard cells and optimized memory instances for popular CPUs, GPUs and DSPs
- Integrated test and repair solution delivers higher test quality and yield, while lowering overall chip areas