The IQ compression IP core is a silicon agnostic implementation of a compression and de-compression scheme enabling doubling data capacity on exiting CPRI or Ethernet based links or alternatively running lower speed links between remote radio units and baseband cards with the same radio ressource capacity. The compression IP handles any radio channel bandwidth and operates on time-domain IQ samples with minimal loss.
The IP core enables quick and reliable deployment of compression and de-compression at both radio and baseband side and can be configured to handle any kind of fronthaul implementation.
- Delivering Performance
- Compression better than 50%
- Supports aggregated data rates up to 491.52 Ms/s
- Very low micro-second latency
- Very low EVM degradation
- Easy to use
- Matlab test environment can be provided
- Easy configurable
- Silicon Agnostic
- Designed in VHDL-93 and targeting any RTL implementation such as ASICs, ASSPs and FPGAs.
- Enables lower capacity backhaul like microwave links
- Improves throughput on existing microwave links
- Enables reduction of fiber connections between radio site and baseband site
- IP core: RTL is delivered as source code (encrypted or un-encrypted VHDL) or netlist
- User Manual: Describing among others top Level I/O’s definition, registers, clocking strategy, functional description
- Test bench: Matlab test bench
- Test cases: Delivered with System Verilog UVM
- Connecting RU with BU
- Chip-to-chip RU systems
- Test Systems
Block Diagram of the I/Q Compression and De-compression for CPRI links