The I2S Audio Interface provides a bidirectional, synchronous, serial interface to off-chip audio devices. It complies with the Inter-IC Sound (I2S) bus specification from Philips Semiconductor (I2S bus specification; February 1986, revised June 5, 1996) and is the same I2S Audio Interface IP proven in high-volume devices from National Semiconductor.
The host interface of the I2S Audio Interface complies with the AMBA 2.0 APB protocol. Control registers provide CPU control of master or slave mode, audio data format, data word length, bit clock generation, word select signal resolution, FIFO threshold levels, and enabling/disabling interrupts. Status registers provide interrupt and FIFO status.
Transfer of audio data to/from the host system can be either interrupt-driven or through DMA to reduce CPU utilization. In both cases, four 8-word-deep FIFOs with programmable threshold levels provide storage of transmit/receive data for the left and right channels. APB-accessible registers provide read or write access to each of the four FIFOs.
The I2S bus interface of the I2S Audio Interface is a set of unidirectional signals that connect to chip I/O pads to form the off-chip I2S bus signals: serial clock (I2SCLK), word select (I2SWS), serial data in (I2SSDI), and serial data out (I2SSDO). To reduce chip-level pin count, the I2S bus interface signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.
- Can operate as master or slave in several configurations
- Master or slave mode as transmitter
- Master or slave mode as receiver
- Master or slave mode as transmitter and receiver
- Master mode as controller (does not transmit or receive data)
- Bidirectional operation through two unidirectional serial data lines
- Supports audio data widths from 8 to 24 bits
- Supports multiple audio data formats
- I2S format
- Left Justified
- Right Justified
- Programmable word select resolution (8–32 clock cycles) in master mode
- Four reference clock sources selectable for bit clock generation with programmable clock divider
- Interrupt-driven or DMA operation
- Four 8-word FIFOs (left/right; transmit/receive)
- Programmable FIFO threshold levels for interrupt or DMA request generation
- Additional interrupts for transmit FIFO underrun and receive FIFO overrun with separate enables
- Freeze/suspend operation for system debug support
- Local clock gating for minimal power consumption