IGMDLRX01A is an asynchronous read and synchronous write ULVT periphery two port register file compiler (2PRF). It is developed with TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different combinations of words, bits, and column-selected number (MUX) could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMDLRX01A compiler is capable of providing suitable asynchronous 2PRF instances models within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as the setup/hold times and minimum high/low pulse widths requirements are satisfied. This allows a more flexible clock falling edge during each operation.
- Pins and metal layers
- – 1P4M (1X_h_1Xa_v_1Ya_h): 4 metal layers used and top metal is MYa
- – Power mesh supported with M4 pins
- – High Current TSMC 8T 0.053um2 SRAM bit cell
- – Full-customized design to optimize for performance, power and area
- – One port for synchronous write operation and the other port for asynchronous read operation
- – Support word write and bit write operations
- – Column Mux options for the best aspect ratio
- – No write through
- – ULVT periphery
- – Memory control pins for read and write
- – Operating frequency up to 2GHz among all specified operating (characterized) corners
- – Frequently used EDA model support