The Trilinear Technologies AVP-27 Image Scaler provides high quality results for demanding video applications. The AVP-27 balances complexity and resource usage for an optimal solution capable of generating images suitable for display in large screen applications. Host programmable scaler parameters allows the AVP-27 to be configured once on power up or reconfigured on the fly for input specific optimizations.
Using a multiple tap Finite Impulse Response (FIR) based algorithm provides high quality results using time tested frequency domain analysis of the scaling function. Developed in Matlab, the AVP-27 is provided with a complete range of filter settings including ultra-sharp and movie modes. Custom filters can be generated by customers and loaded into the core for testing. Additional non-linear processing elements may be enabled or disabled as needed.
The AVP-27 is delivered as either a technology specific firm core a technology independent soft core and may be implemented on both FPGA and ASIC platforms. The Trilinear Technologies’ development process allows for the migration if soft cores from FPGA to ASIC for prototyping and production solutions with no core modifications. The AVP-27 core offers an optimal solution for both technologies without the typical limitations of performance in ASIC form and area in FPGA form. This flexibility is achieved through a state of the art internal architecture and best in class design practices.
The AVP-27 core ships with a complete ‘C’ reference driver and a fully documented API. The core is available on the Trilinear Technologies’ Vantage Development platform. This FPGA based reference system provides a complete development environment for core evaluation as well as early software development.
- Real time, frequency domain based image scaling
- Programmable coefficients
- Zero CPU overhead after initial configuration
- Variable scale factor with single pixel increments
- Core Details
- Programmable coefficient memory for application specific adjustment
- 16X downscale
- 128X upscale
- AMBA APB-3 Slave Interface
- 24, 30, 36-bit pixel support
- Reference Software
- ‘C’ source code included
- Complete device driver
- Real time video player
- Fully documented API
- FPGA Development Platform
- 32-bit MCU based system
- Real time video input
- Includes the AVP-27 Image Scaler, DDR-2 system and display controller
- DVI digital output
- HDL source files for the function design
- HDL source files for block level and top level testing
- Functional specification
- Timing constraints summary document
- Generic SRAM simulation models
- C Reference Driver
Block Diagram of the Image Scaler IP Core