PCMCIA Host & Device Controller IP Core

The PCMCIA Host & Device Controller core provides an efficient and easy-to-use interface to devices that are PCMCIA card 2.1 compliant. The PCMCIA Controller generates read/write cycles for attribute memory, common memory, and I/O modes. The PCMCIA Controller is designed to interface to the processor through a CoreFrame® bus interface. The CoreFrame bus interface is a non-pipelined interface incorporating address, data, read strobe, write strobe, and a wait signal. Interrupt status and masking registers are provided to enable polled or interrupt driven firmware to service the interrupts. Particular events on the PCMCIA card interface can be programmed to generate an interrupt to the processor. The core includes programmable timing control registers to support a wide range of operating frequencies. PC cards can be memory mapped to simplify firmware.