Phase-Locked Loop (PLL) provides a clock multiplier and/or de-skew circuit to generate a stable, high-speed clock from an external slower clock signal. Generic PLL consists of a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low Pass Filter (LPF), the programmable dividers, and all associated supporting circuitry. PLL facilitates the clock multiplications from the stable crystal oscillator source.
In order to reduce the EMI of PCB, most designers operate an off-chip low-frequency crystal oscillator or other clock signal, such as the clock source. When the clock is used in the chip, PLL will be used as a clock generator or a so-called â€œFrequency synthesizerâ€. Its purpose is to generate a high-frequency clock for the core logic from a lower external input clock. Generally, the external clock will be a â€œ Crystal oscillator-basedâ€ or â€œOscillator-basedâ€ component.
Innopower provides a special PLL, miniPLL™, which is completely integrated into the I/O region without taking any core area space.
The Spread Spectrum Clock Generator (SSCG) is capable of generating the spreading output clock. Compared with a non-spreading clock, SSCG can produce a relatively low EMI (ElectroMagnetic Interference) clock. By using the Spread Spectrum Clock Generator, the peak of the emission can be reduced; moreover, the peaks of the harmonics spectrum and the fundamental frequency can be reduced. The SSCG contributes the reduction of radiation even the rest of the EMI reduction, such as shields, by-pass capacitors, chip coils, or ferrite beads, are not used. Applying SSCG will enable the cost-reduction of the end-products.
- Low jitter clock output
- m-bit programmable pre-divider
- n-bit programmable loop divider
- Built-in isolated PLL testing circuit
- Power-down mode and bypass mode
- Built-in loop filter
- No external component required