As part of INSIDE Secure's award-winning silicon Intellectual Property (IP) product portfolio, the SafeXcel-IP-32 - AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include encryption and decryption cores.
Designed for fast integration, low gate count, and maximum performance, the SafeXcel IP AES Accelerators provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
- Supported key sizes: 128, 192, and 256 bits.
- Includes key scheduling hardware.
- Fully synchronous design
- High-speed AES solution
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
- SafeXcel-IP-32 Hardware Reference and Programmer Manual
- SafeXcel-IP-32 Integration Manual
- SafeXcel-IP-32 Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Synthesis scripts
- EIP-32b (encrypt&decrypt) / EIP-32c (encrypt only)
- 6976 Mbit/s
- 545 MHz
- 34.3 k gates / 20.3 k gates
- EIP-32d (encrypt&decrypt) / EIP-32e (encrypt only)
- 2660 Mbit/s
- 640 MHz
- 19.0 k gates / 13.3 k gates
- EIP-32f (encrypt&decrypt) / EIP-32g (encrypt only)
- 1574 Mbit/s
- 640 MHz
- 13.8 k gates / 10.5 k gates