As part of INSIDE Secure's award-winning silicon Intellectual Property (IP) product portfolio, the SafeXcel-IP-75 True Random Number Generators (TRNG) provide semiconductor designers with a silicon-proven solution that has been deployed in SafeNet's leading VPN accelerator chips, as well as in several chips manufactured by SafeNet semiconductor customers. The SafeXcel IP True Random Number Generators are typically deployed in semiconductors for secure data communications, secure electronic transactions, and secure data storage. They are, for example, used for generation of keys, initialization vectors, cookies, and nonces. The TRNG's can also be used for statistical sampling, timers in communications protocols, as well as noise generation.
- Shot noise based non-deterministic Random Number Generator
- Optional ANS X9.31 (Appendix A.2.4) compliant 3-key 3-DES post-processor to meet the NIST requirements of FIPS 140-2
- Redundant ‘Fail-Safe’ design with self-test circuits
- Reliable Free Running Oscillator implementation with auto-tuning across PVT range of up to a factor 10 between worst case and best case delay
- Output ready interrupt
- Alarm count overflow and auto-tuning error interrupt
- Optional separate (fixed frequency) sampling clock to allow variable frequency system clock
- Start up time can be controlled between 28 and 225 sampling clock cycles to adapt entropy accumulation time to basic entropy generation rate (which varies with the implementation technology)
- Selectable sequential or parallel operation of FROs to reduce power consumption or speed up initialization
- Glitch-free starting and stopping of FRO-generated clocks
- Debug outputs to allow monitoring of internal operations.
- Silicon-proven implementation.
- Fast and easy to integrate into SoCs.
- Flexible layered design.
- Software support available:
- Generic driver library
- Configurations with/without post-processor and single/dual clocks.
- World-class technical support.
- SafeXcel-IP-75 Hardware Reference Manual
- SafeXcel-IP-75 Integration Manual
- SafeXcel-IP-75 Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Synthesis scripts
- EIP-75a (no post-processor)
- 93 Mbit/sec
- 300 MHz
- 6.6 k gates
- EIP-75b (with post-processing)
- 90 MBit/sec
- 300 MHz
- 15.3 k gates