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Silicon IP Catalog
Interface Controller & PHY
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Interface Controller & PHY IP Core

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Interface Controller & PHY IP Listing

1836 IP Cores (161 - 200)

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MIPI D-PHY Transmitter in Samsung 28nm FDSOI

The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The IP can be configured as a MIPI Master ...

161
MIPI D-PHY CSI Transmitter in TSMC 28nm HPC+

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized ...

1 Testimonial
Kent Goodin, VP Engineering, GEO Semiconductor, Inc.

162
MIPI D-PHY Universal 4 Lane 2.5Gbps

The MXL-D-PHY-UNIV-T-65GP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1. The PHY can be configured as ...

163
USB 2.0 Full/Low-Speed Device Core

The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality with SRP (Session Request Protocol) in an ...

164
USB 2.0 High/Full-Speed Device Core

The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functionality with SRP (Session Request Protocol) ...

165
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 4.0 operates at 2.5Gbps, 5Gbps, ...

166
MIPI D-PHY v1.2/LVDS/TTL combo PHY(supporting CSI/DSI)

The INNO_MIPI D-PHY is a MIPI® V1.0 compliant solution available in both Tx or Rx configuration. Each PHY supports high-speed 1.5 GHbps data transfer combined with a MIPI® low-power bi-directional ...

167
4-lane MIPI CSI2 serial video transmitter for FPGA implementations

Compact serial video tranmitter comlying with MIPI CSI2 standrad, supporting from 1 to 4 data lanes and optimized for FPGA implementatons

168
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock

The Extended MIPI CSI2 Serial Video Receiver IP core is designed to support those trends, and, at the same time, work with a relatively slow clock rate, processing several pixels per clock. ...

169
HDMI 2.0a IP Core

The Bitec HDMI 2.0a IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using ...

170
1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)

The AlphaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is a high-performance, low-power, DSP-based PHY. It is a highly configurable IP that supports all leading edge NRZ and PAM data center ...

171
10-112Gbps Low Power PHY

The Alphawave ChipCORE VSR MSS IP is a VSR optimized SerDes architecture that supports data center standards up to 112Gbps PAM4. The ChipCORE is a companion IP to the AlphaCORE IP, delivering ...

172
25-112Gbps Short-Reach PHY

The Alphawave DieCORE delivers the world’s highest density, lowest power die-to-die connectivity solution for MCMs based on IEEE XSR/USR serial standards. The DieCORE is a companion IP ...

173
1 – 33Gbps Die-to-Die SerDes PHY

The AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links.

174
1 – 33Gbps C2C SerDes PHY

The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links. The AXLinkIO C2C IP from AnalogX is compatible to several protocols ...

175
1-33Gbps C2C SerDes PHY

The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links. The AXLinkIO C2C IP from AnalogX is compatible to several protocols ...

176
32-bit PCI Bus Master/Target

32-bit PCI Bus Master/Target with configurable FIFOs and AHB back end

177
Bi-directional AMBA AHB/AHB bridge

The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any frequency ratio between the two interconnected ...

178
Uni-directional AMBA AHB to AHB bridge

The Uni-directional AHB to AHB bridge is used to connect two AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected through a pair consisting of an AHB slave ...

179
USB 2.0 Host Controller

The USB 2.0 Host Controller core (GRUSBHC) provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic. ...

180
USB 2.0 Device Controller

The Universal Serial Bus Device Controller provides a USB 2.0 function interface accessible from an AMBA-AHB bus interface. The core must be connected to the USB through an external PHY compliant ...

181
Mil-Std-1553B/AS15531 Interface

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM). The core is connected ...

182
HDMI 1.4 Transmitter PHY/Controller

The INNOSILICON low power mixed signal HDMI-IPTM Transmitter PHY/controller provides a complete HDMI 1.4b standard compliant transceiver interface solution for delivering video and audio streams ...

183
USB 3.0 femtoPHY in GlobalFoundries (28nm)

The Synopsys DesignWare® USB 3.0 femtoPHY and DesignWare® USB-C 3.0 femtoPHY provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications ...

184
FlexNoC AI Package

Arteris IP FlexNoC AI Package accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and optimize the networks while efficiently implementing ...

185
SD 4.0 Device Controller

The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP core is targeted to develop a range of memory ...

186
MIPI D-PHY in GlobalFoundries 40nm Automotive Process

Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing ...

187
USB2.0 Host Transceiver PHY

USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceivers and is compliant with the USB 2.0 Specification ...

188
MIPI UniPro Controller - v1.6

The MIPI UniPro Controller IP core is fully compliant to UniPro Specification, it implements the UniPro Physical Adapter, Data Link, Network,and Transport layers. A variety of high-performance ...

189
USB 3.0 Device Controller

The USB 3.0 Device Controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0. The USB 3.0 Device provides a dedicated ...

190
MIPI D-PHY Transmitter - Designed for SMIC 130nm

The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY Designed for SMIC 130nm. The IP ...

191
MIPI D-PHY Receiver

The MXL-DPHY-CSI2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI ...

1 Testimonial
Mike Hopton, VP Operations & GM Toronto, GEO Semiconductor, Inc.

192
MIPI D-PHY Receiver

The MXL-DPHY-CSI2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave ...

193
USB 3.0 SATA 3.0 PCIe 2.0 XAUI MultiPHY

The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2, USB3.0 and XAUI with full compliance. It is available in multiple technologies today and can be ported ...

194
RapidIO Controller with V4.0 Support

The RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The The RapidIO Controller can be used as a Host or device. The RapidIO Controller when used along with the RapidIO ...

195
USB 2.0 USB IF high-speed certified device (USB20SR)

The USB20SR is a USB 2.0 USB IF high-speed certified device IP Core. The core is RAM based with 32-bit Avalon interface and supports ULPI interface and Software Enumeration. It supports both ...

196
USB 2.0 Device with FIFO Interface (USB20HF)

The USB 2.0 Device with FIFO Interface (USB20HF) IP Core supports ULPI interface with Bulk IN and Bulk OUT endpoints. The core supports three preconfigured endpoints Control, Bulk IN, and Bulk ...

Evaluate this IP for FREE!

197
USB 2.0 Host Controller

The USB 2.0 Host Controller (USB20HC) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. The core supports High Speed (480 Mbit/s) mode, Full Speed (12 Mbit/s) ...

198
eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface

Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel FPGA built-in 10 Gbps transceiver. It is a one-stop solution for all USB requirements ...

199
1 to 4 Lane Serial Video Transmitter For MIPI CSI2

The SVT-CS4AP1 supports MIPI CSI2 over MIPI D-PHY.

200

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