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Silicon IP Catalog
Interface Controller & PHY
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Interface Controller & PHY IP Core

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Interface Controller & PHY IP Listing

1936 IP Cores (161 - 200)

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Display Stream Compression (DSC 1.2) Decoder

The Display Stream Compression (DSC) standard from the Video Electronics Standards Association (VESA) offers visually lossless compression for high definition (HD) video in broadcast, automotive, ...

161
USB 3.0 femtoPHY in GlobalFoundries (28nm)

The Synopsys DesignWare® USB 3.0 femtoPHY and DesignWare® USB-C 3.0 femtoPHY provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications ...

162
FlexNoC AI Package

Arteris IP FlexNoC AI Package accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and optimize the networks while efficiently implementing ...

163
SD 4.0 Device Controller

The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP core is targeted to develop a range of memory ...

164
MIPI D-PHY in GlobalFoundries 40nm Automotive Process

Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing ...

165
USB2.0 Host Transceiver PHY

USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceivers and is compliant with the USB 2.0 Specification ...

166
MIPI UniPro Controller - v1.6

The MIPI UniPro Controller IP core is fully compliant to UniPro Specification, it implements the UniPro Physical Adapter, Data Link, Network,and Transport layers. A variety of high-performance ...

167
USB 3.0 Device Controller

The USB 3.0 Device Controller implements all of the digital layers defined by the USB 3.0 Specification and is fully backward compatible with USB 2.0. The USB 3.0 Device provides a dedicated ...

168
UFS Host 3.0 Prototyping Kit (HDK )Total IP in a Box

Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface. UFS is designed to be the most advanced specification for flash memory based storage ...

169
UFS Host 2.1 Prototyping Kit (HDK )Total IP in a Box

Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface. UFS is designed to be the most advanced specification for flash memory based storage ...

170
MIPI D-PHY Transmitter - Designed for SMIC 130nm

The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY Designed for SMIC 130nm. The IP ...

171
MIPI D-PHY Receiver

The MXL-DPHY-CSI2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI ...

1 Testimonial
Mike Hopton, VP Operations & GM Toronto, GEO Semiconductor, Inc.

172
MIPI D-PHY Receiver

The MXL-DPHY-CSI2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave ...

173
MIPI M-PHY

The MXL-M-PHY-DIGRF is a high-frequency low-power, low-cost, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY and DigRF. The IP can be used as a physical layer for the ...

174
MIPI D-PHY Transmitter in Samsung 28nm FDSOI

The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The IP can be configured as a MIPI Master ...

175
MIPI D-PHY 4 Lane CSI2-TX 1.2G

The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized ...

1 Testimonial
Gareth Powell, Marketing Manager, Teledyne e2v

176
MIPI D-PHY, CSI-2 TX+ for TSMC40ULP

The MXL-D-PHY-CSI-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous,physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1. The PHY can be configured ...

177
PCIe 4.0 SerDes PHY

The Rambus 16 Gbps PCIe SerDes PHYs is a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical of copper backplanes and long runs of ...

178
PCIe 3/2/1 SerDes PHY

The Rambus 12 Gbps PCIe SerDes PHYs is a general-purpose, high-speed serial link transceiver subsystem that support data rates from 1.25 Gbps to 12 Gbps. Optimized for power and area in high-loss ...

179
USB 2.0 PHY Device/Host/OTG/Hub

The INNOSILICON USB 2.0 OTG PHY is fully compliant with UTMI+ level 3 Rev 1.0 specification. Offering excellent performance combined with a die size up to 30% less than the competition, this ...

180
USB 3.0 SATA 3.0 PCIe 2.0 XAUI MultiPHY

The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2, USB3.0 and XAUI with full compliance. It is available in multiple technologies today and can be ported ...

181
Gen5 PCIe Root Complex Controller with SR-IOV and ARI Support

The PCI Express Root Complex Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The ...

182
RapidIO Controller with V4.1 Support

The RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The The RapidIO Controller can be used as a Host or device. The RapidIO Controller when used along with the RapidIO ...

183
eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface

Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel FPGA built-in 10 Gbps transceiver. It is a one-stop solution for all USB requirements ...

184
1 to 4 Lane Serial Video Transmitter For MIPI CSI2

The SVT-CS4AP1 supports MIPI CSI2 over MIPI D-PHY.

185
Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard

The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC. It receives camera signals in accordance with the MIPI CSI-2 and D-PHY specifications. BitCsi2Rx converts ...

186
I2S IP core

The use of IP cores in ASIC, FGPA and system-on-chip (SoC) designs has become a critical methodology as companies struggle to address the need for rapid prototyping and production. Reusable, ...

187
CML RapidIO SerDes

The use of Rapid IO supporting IP cores speeds the design cycle, increases design quality and allows greater degree of innovation, enabling companies to reduce design costs and create market ...

188
UniPro IP Core

The MIPI UniPro IP core complies with the UniPro specification version 1.4. The MIPI UniPro IP core implements the Physical-Adapter Layer (L.15), Data Link Layer (L2), Network Layer (L3) and ...

189
Serial RapidIO IP Core

The HIP 3300 Serial RapidIO IP solution is a complete high-performance core that incorporates a logical layer, a transport layer, and a physical layer according to the RapidIO specification ...

190
MIPI DSI Peripheral Controller IP Core

The HIP 3510 is a highly configurable, synthesizable digital IP core, used to exchange pixels and command data between a video source (host processor) and a display peripheral. Designed for ...

191
MIPI DSI Host IP Core

HIP 3500 is MIPI DSI Host (TX) IP core. HIP 3500 receives pixel data and commands from the host processor through AXI/AHB interface and sends data to PPI interface. HIP 3500 is highly configurable ...

192
MIPI D-PHY Compliant With CSI-2 And DSI

Arasan delivers you MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing ...

2 Testimonials
David Moloney, Chief Technology Officer at Movidia, Movidia

193
MIPI D-PHY TSMC 130nm

Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing ...

194
MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+

Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without increased signaling clock. It is intended ...

5 Testimonials
Joel Huloux, Chairman of the board of MIPI Alliance, MIPI Alliance

195
MIPI D-PHY / C-PHY Combo IP for TSMC 22nm

Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.2 improves throughput over a bandwidth limited channel, allowing more data without increased signaling clock. It is intended ...

196
MIPI C-PHY and D-PHY Combo

The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 ...

197
FlexNoC Resilience Package IP

For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL ...

198
Cache Coherent Interconnect

For scalable and area-efficient heterogeneous cache coherent systems. Arteris Ncore™ Cache Coherent Interconnect IP implements the same philosophy as our FlexNoC IP: Maximum configurability ...

199
Timing Closure Package

An optional add-on for Arteris® FlexNoC® and Ncore™ interconnect IP that helps automate interconnect timing closure. PIANO provides more and better physical and timing information about ...

200

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