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Silicon IP Catalog
Interface Controller & PHY
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Interface Controller & PHY IP Listing

1841 IP Cores (161 - 200)

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MIPI Compliant D-PHY

The MIPI D-PHY is compliant with the MIPI Alliance Standard for D-PHY. Although it is primarily used for connecting cameras and display devices to a cost processor, it can also be used for many ...

5 Testimonials
Kent Goodin, VP Engineering, GEO Semiconductor, Inc.

161
MIPI D-PHY Transmitter - Designed for TSMC 28nm

The MXL-PHY-MIPI-UNIVERSAL-T-028 is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The MIPI D-PHY Transmitter ...

162
MIPI D-PHY Transmitter - Designed for SMIC 130nm

The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY Designed for SMIC 130nm. The IP ...

163
MIPI D-PHY Transmitter

The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master ...

164
MIPI D-PHY Transmitter - Designed for TSMC 40nmLP

The MXL-DPHY-CSI2-TX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI ...

165
MIPI D-PHY Receiver in TSMC 65nm LP

The MIPI D-PHY Receiver is a high-frequency low-power, low-cost, sourcesynchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and ...

166
MIPI D-PHY Receiver in TSMC 40nm LP

The MXL-PHY-DSI-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave optimized ...

1 Testimonial
CG Kim, VP of Engineering, Anapass, Inc.

167
Aurora-like 8b/10b @3Gbps for ALTERA Devices

The Aurora-like IP Core is based on ALTERA FPGA and enables interoperability between VIRTEX 6 LXT XILINX and STRATIX IV GX and STRATIX V GX ALTERA FPGA.

168
Aurora-like 64b/66b @14Gbps for ALTERA Devices

The 14Gbps Aurora-like IP Core is based on ALTERA FPGA and enables interoperability between XILINX and ALTERA FPGA.

169
Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto

The Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based support for for IEEE 1588 V1 and V2. It ...

170
MIPI M-PHY Designed For TSMC 28nm

ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of ...

171
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto

The 10 Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based support for for IEEE 1588 V1 and V2. ...

172
MIPI M-PHY - UMC 40nm

MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of ...

173
UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8

Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) ...

174
SD 4.1 UHS-II PHY for TSMC 12nm FF

The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interfaces with larger capacities and faster access ...

175
MIPI M-PHY G4 Designed For TSMC 28nm HPC+

ACS-AIP-MPHY-28HPC+ MIPI Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of ...

176
USB 2.0 Full/Low-Speed Device Core

The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality with SRP (Session Request Protocol) in an ...

177
USB 2.0 Full/Low-Speed Embedded Host Controller

The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality in an embedded system. It provides an ease ...

178
USB 2.0 High/Full-Speed Device Core

The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functionality with SRP (Session Request Protocol) ...

179
USB 2.0 High/Full/Low-Speed Embedded Host Controller

The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functionality in an embedded system. It provides ...

180
USB 2.0 OTG High/Full/Low-Speed Dual Role Core

The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and host functionality in an embedded system. ...

181
USB 2.0 OTG Full/Low-Speed Dual Role Core

The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host functionality in an embedded system. It ...

182
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 4.0 operates at 2.5Gbps, 5Gbps, ...

183
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 5.0 operates at 2.5Gbps, 5Gbps, ...

184
MIPI D-PHY v1.2/LVDS/TTL combo PHY(supporting CSI/DSI)

The INNO_MIPI D-PHY is a MIPI® V1.0 compliant solution available in both Tx or Rx configuration. Each PHY supports high-speed 1.5 GHbps data transfer combined with a MIPI® low-power bi-directional ...

185
4-lane MIPI CSI2 serial video transmitter for FPGA implementations

Compact serial video tranmitter comlying with MIPI CSI2 standrad, supporting from 1 to 4 data lanes and optimized for FPGA implementatons

186
Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane

The Low Latency Interlaken core is compliant with the Interlaken 1.2 and Interlaken look-aside 1.1 specifications. The System BusWidth, Core BusWidth, and Lane Count are configurable. The ...

187
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock

The Extended MIPI CSI2 Serial Video Receiver IP core is designed to support those trends, and, at the same time, work with a relatively slow clock rate, processing several pixels per clock. ...

188
DisplayPort 1.4 IP Core

DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, DELL, Apple etc) DisplayPort is not hindered ...

189
HDMI 2.0a IP Core

The Bitec HDMI 2.0a IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using ...

190
V-by-One HS IP core

V-by-One®HS was developed by THine Electronics, Inc. to support the higher frame rates and the higher resolutions required by advancing FPD technologies, while reducing costs and time to market. ...

191
VESA Display Stream Compression (DSC) IP Core

Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offer a ...

192
1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)

The AlphaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is a high-performance, low-power, DSP-based PHY. It is a highly configurable IP that supports all leading edge NRZ and PAM data center ...

193
10-112Gbps Low Power PHY

The Alphawave ChipCORE VSR MSS IP is a VSR optimized SerDes architecture that supports data center standards up to 112Gbps PAM4. The ChipCORE is a companion IP to the AlphaCORE IP, delivering ...

194
25-112Gbps Short-Reach PHY

The Alphawave DieCORE delivers the world’s highest density, lowest power die-to-die connectivity solution for MCMs based on IEEE XSR/USR serial standards. The DieCORE is a companion IP ...

195
1 – 33Gbps Die-to-Die SerDes PHY

The AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links.

196
1 – 33Gbps C2C SerDes PHY

The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links. The AXLinkIO C2C IP from AnalogX is compatible to several protocols ...

197
1-33Gbps C2C SerDes PHY

The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links. The AXLinkIO C2C IP from AnalogX is compatible to several protocols ...

198
Hardware Offload Engine IP Core for ARINC-818

The New Wave Design and Verification (New Wave DV) ARINC-818 core provides a complete hardware IP solution for the ARINC-818 protocol. The core provides full specification compliance, hardware-based ...

199
HDMI 1.4 Transmitter PHY/Controller

The INNOSILICON low power mixed signal HDMI-IPTM Transmitter PHY/controller provides a complete HDMI 1.4b standard compliant transceiver interface solution for delivering video and audio streams ...

200

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