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Silicon IP Catalog
Interface Controller & PHY
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Interface Controller & PHY IP Listing

1850 IP Cores (161 - 200)

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MIPI D-PHY Transmitter - Designed for TSMC 40nmLP for Automotive

The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP can be configured as a ...

161
MIPI C-PHY/D-PHY Combo IP

The MXL-CPHY-DPHY-DSI-TX is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display interface DSI. The High-Speed signals have ...

1 Testimonial
Jeff Lukanc, Senior Director of Interface Solutions, Synaptics

162
MIPI CSI2 Transmit Controller

The MIPI CSI-2 Transmit Controller facilitates transmission over a standard high-speed unidirectional serial interface between CSI-2 Transmitter and Receiver. The receiver is typically a host ...

163
MIPI CSI2 v1.3 Transmit Controller

The MIPI CSI-2 v1.3 Transmit Controller facilitates transmission over a standard high-speed unidirectional serial interface between CSI-2 Transmitter and Receiver. The receiver is typically ...

164
Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto

The Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based support for for IEEE 1588 V1 and V2. It ...

165
MIPI M-PHY Designed For TSMC 28nm

ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of ...

166
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto

The 10 Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based support for for IEEE 1588 V1 and V2. ...

167
MIPI M-PHY - UMC 40nm

MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of ...

168
UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8

Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) ...

169
SD 4.1 UHS-II PHY for TSMC 12nm FF

The rapid proliferation of high-performance mobile and handheld devices has resulted in increasing requirements for non-volatile memory. Memory interfaces with larger capacities and faster access ...

170
MIPI M-PHY G4 Designed For TSMC 28nm HPC+

ACS-AIP-MPHY-28HPC+ MIPI Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of ...

171
MIPI D-PHY Receiver

The MXL-DPHY-CSI2-RX-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI ...

1 Testimonial
Mike Hopton, VP Operations & GM Toronto, GEO Semiconductor, Inc.

172
MIPI D-PHY Receiver

The MXL-DPHY-CSI2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave ...

173
MIPI M-PHY

The MXL-M-PHY-DIGRF is a high-frequency low-power, low-cost, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY and DigRF. The IP can be used as a physical layer for the ...

174
USB 2.0 Full/Low-Speed Device Core

The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality with SRP (Session Request Protocol) in an ...

175
USB 2.0 Full/Low-Speed Embedded Host Controller

The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality in an embedded system. It provides an ease ...

176
USB 2.0 High/Full-Speed Device Core

The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functionality with SRP (Session Request Protocol) ...

177
USB 2.0 High/Full/Low-Speed Embedded Host Controller

The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functionality in an embedded system. It provides ...

178
USB 2.0 OTG High/Full/Low-Speed Dual Role Core

The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and host functionality in an embedded system. ...

179
USB 2.0 OTG Full/Low-Speed Dual Role Core

The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host functionality in an embedded system. It ...

180
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 4.0 operates at 2.5Gbps, 5Gbps, ...

181
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 5.0 operates at 2.5Gbps, 5Gbps, ...

182
MIPI D-PHY v1.2/LVDS/TTL combo PHY(supporting CSI/DSI)

The INNO_MIPI D-PHY is a MIPI® V1.0 compliant solution available in both Tx or Rx configuration. Each PHY supports high-speed 1.5 GHbps data transfer combined with a MIPI® low-power bi-directional ...

183
4-lane MIPI CSI2 serial video transmitter for FPGA implementations

Compact serial video tranmitter comlying with MIPI CSI2 standrad, supporting from 1 to 4 data lanes and optimized for FPGA implementatons

184
Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane

The Low Latency Interlaken core is compliant with the Interlaken 1.2 and Interlaken look-aside 1.1 specifications. The System BusWidth, Core BusWidth, and Lane Count are configurable. The ...

185
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock

The Extended MIPI CSI2 Serial Video Receiver IP core is designed to support those trends, and, at the same time, work with a relatively slow clock rate, processing several pixels per clock. ...

186
DisplayPort 1.4 IP Core

DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, DELL, Apple etc) DisplayPort is not hindered ...

187
HDMI 2.0a IP Core

The Bitec HDMI 2.0a IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices. Supporting pixel clocks to 600Mhz, the IP core allows ULTRA HD designs while using ...

188
V-by-One HS IP core

V-by-One®HS was developed by THine Electronics, Inc. to support the higher frame rates and the higher resolutions required by advancing FPD technologies, while reducing costs and time to market. ...

189
VESA Display Stream Compression (DSC) IP Core

Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offer a ...

190
1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)

The AlphaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is a high-performance, low-power, DSP-based PHY. It is a highly configurable IP that supports all leading edge NRZ and PAM data center ...

191
10-112Gbps Low Power PHY

The Alphawave ChipCORE VSR MSS IP is a VSR optimized SerDes architecture that supports data center standards up to 112Gbps PAM4. The ChipCORE is a companion IP to the AlphaCORE IP, delivering ...

192
25-112Gbps Short-Reach PHY

The Alphawave DieCORE delivers the world’s highest density, lowest power die-to-die connectivity solution for MCMs based on IEEE XSR/USR serial standards. The DieCORE is a companion IP ...

193
1 – 33Gbps Die-to-Die SerDes PHY

The AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links.

194
1 – 33Gbps C2C SerDes PHY

The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links. The AXLinkIO C2C IP from AnalogX is compatible to several protocols ...

195
1-33Gbps C2C SerDes PHY

The AXLinkIO C2C IP utilizes the silicon-proven AXLinkIO transceiver architecture for short-reach type of channel links. The AXLinkIO C2C IP from AnalogX is compatible to several protocols ...

196
32-bit PCI Bus Master/Target

32-bit PCI Bus Master/Target with configurable FIFOs and AHB back end

197
USB 2.0 Host Controller

The USB 2.0 Host Controller core (GRUSBHC) provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic. ...

198
USB 2.0 Device Controller

The Universal Serial Bus Device Controller provides a USB 2.0 function interface accessible from an AMBA-AHB bus interface. The core must be connected to the USB through an external PHY compliant ...

199
HDMI 1.4 Transmitter PHY/Controller

The INNOSILICON low power mixed signal HDMI-IPTM Transmitter PHY/controller provides a complete HDMI 1.4b standard compliant transceiver interface solution for delivering video and audio streams ...

200

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