The S3AD1M12BC18 is a low-power, 4-input 12-bit ADC IP
with a sampling rate up to 1.083MS/s.
The ADC employs a high-performance sample-and-hold (S/H)
circuit together with a two-stage algorithmic architecture and
digital error correction.
A temperature sensor core is also included thus allowing the
S3AD1M12BC18 to be employed as a 12-bit temperature-to digital converter.
- TSMC 0.18um Mixed Signal and RF Process
- 1.8V and 3.3V Supplies
- 12-bit 1MS/s ADC with 4 Inputs and T-Sensor Core
- 4 Multiplexed Single-Ended or Differential Inputs
- 3.0Vpp Input Range in Single-Ended Mode
- 3.0Vppdiff Input Range in Differential Mode
- Integrated Temperature Sensor
- -40 to +125ºC Temperature Range
- Absolute error after calibration: ±3ºC
- Dynamic Element Matching (DEM) Algorithm
- Fin= 200kHz Typ.
- DNL= ±0.5LSB Typ.
- INL= ±1.0LSB Typ.
- SNR= 63.5dB Typ.
- THD= -80dB Typ.
- SNDR= 63.2dB Typ.
- ENOB= 10.2-bit Typ.
- Low-Power: 4.25mW at 1.083MS/s
- Small Die Area = 0.364mm2
- This 12-bit ADC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL typ.
- Dynamic performance highlights considering an input signal with 200kHz frequency, 1.083MS/s sampling rate for the ADC core, include SNR of 63.5dB and SNDR of 63.2dB, yielding 10.2ENOB performance.
- Auxiliary circuits comprising a bandgap reference circuit, current biasing and reference buffers with internal decoupling are also included.
- The S3AD1M12BC18 can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
- Multi-sensing environment conversion
- Industrial control
Block Diagram of the IoT: 12-bit 1MS/s ADC with 4 Inputs and T-Sensor