The UDP/IP Hardware Stack / UDP Off-load Engine (UOE) has low latency performance targeting 10/40 GbE high-frequency trading systems. The UDP/IP Hardware Stack / UDP Off-load Engine (UOE) is a Verilog SoC IP Core targeting Xilinx Virtex 7 and Altera Stratix V FPGAs.
- 10/100/1000 MbE or 10/40 GbE wire-line performance with ultra-low latency
- Address Resolution Protocol (ARP) Packet Processor (client/server) with 4-16 entry ARP cache
- VLAN Support
- Internet Protocol (IP) Packet Processor:
- IP & ICMP (Internet Control Message Protocol) Protocol
- Host IP address filter, IP header checksum check & generator, user-selectable Maximum Transmission Unit (MTU), Unicast & Multicast Packet support
- Contact Digital Blocks for Compliance with IETF IPv4/IPv6 RFCs
- User Datagram Protocol (UDP) Packet Processor:
- Support for up to 256 UDP Ports
- UDP header checksum check & generator
- Contact Digital Blocks for Compliance with IETF UDP RFCs
- High Speed Data Interface to user Host Application:
- 10 GbE: 64-bit @ 156.25 MHz AXI4-Stream or Avalon-ST
- 40 GbE: 128-bit @ 312.50 MHz AXI4-Stream or Avalon-ST
- Host set-up & control via Control & Status Registers and Interrupt Controller
- 32-bit @ user clock rate AXI4-Lite or Avalon-MM
- PHY Controller – control interface to user Host Application
- Pipeline, High Clock Rate, Low Latency architecture & design
- Fully-synchronous, synthesizable RTL Verilog SoC IP core
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the UDP/IP Hardware Stack / UDP Off-load Engine (UOE)